Memory performance
Memory subsystem performance doesn't always track with real-world applications, but it's a good place to start.


Memory controllers don't always handle four DIMMs gracefully, so we popped an additional two memory modules into each system for another round of tests. In these tests, we had to back off to a 2T command rate for the nForce and DDR3-equipped X38 systems. This is common adjustment for four-DIMM configurations.


The following latency graphs are a little indulgent, so I won't be offended if you skip them. They show access latencies across multiple block and step sizes, painting a fuller picture of memory controller performance with each chipset. I've arranged the graphs in order of highest latency to lowest. Yellow represents L1 cache, light orange is L2, and dark orange is main memory.






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