Shrinking down
One of the advantages of the Saratoga County location is its relative proximity to key research partners, including IBM's 300 mm fab in East Fishkill, New York and the College of Nanoscale Science and Engineering of the University at Albany. AMD has long worked with IBM and other members of IBM's collaborative technology alliance, and GlobalFoundries continues to participate in that R&D network. The alliance conducts early-stage research and develops new process technologies, taking them to production readiness. Most of that work takes place in IBM's East Fishkill location, and GlobalFoundries has a team of over 70 people working there now. John Pellerin, GlobalFoundries' Director of R&D, says the current agreement runs with IBM though 2015 and includes development of bulk silicon technologies, as well as SOI.

Already, 32nm technology is deep in development, in both SOI and bulk variants. Like the AMD/GlobalFoundries 45nm process, the 32nm process will use immersion lithography to enable smaller geometries. In addition, 32nm will see the introduction of the alliance's "gate first" version of high-K/metal gate technology, along with an ultra-low-k insulator made possible by a porous material. Both changes should improve performance and reduce power consumption, if they work as intended, although the company cited no specific targets for overall performance or power improvements at 32nm.

Pellerin said the first 32nm SRAM test chips were run in Dresden in the fourth quarter of 2008. GlobalFoundries expects to accept tape-outs in late 2009, and production is on schedule for early 2010.

The next step beyond that, at least for bulk silicon, is a 28nm "half-node" process. This slightly smaller process should be an easy conversion from 32nm for any existing GlobalFoundries customers, and it's projected to achieve 40% higher performance and 20% lower power consumption than a comparable 45nm process.

Pellerin names a handful of technologies as possible foundations for subsequent generations of fab tech, including 3D ICs that allow the stacking of components, a new transistor structure called multi-gate FinFET, EUV lithography, and computational lithography. Further out, possibilities like carbon nanotubes and molecular self-assembly enter the conversation, although Pellerin admits such talk is a bit tongue-in-cheek at present.

But perhaps only a bit. One of the first EUV lithography tools in the world is located not far from the future site of Fab 2, at the College of Nanoscale Science and Engineering of the University at Albany. The CNSE is a highly distinctive institution that brings together the academy, employees from a range of companies in the semiconductor industry (including the major tool makers and many members of the IBM alliance), and government. With 80,000 square feet of clean rooms, the CNSE is engaged in everything from very early-stage, nano-scale research to chip prototyping, all while granting degrees. Many elements of the next-generation process technologies used by GlobalFoundries and the other members of the IBM alliance are likely to be developed there.