Dual channels at last: VIA's PT880
VIA fought a long, valiant PR effort on the behalf of single-channel memory designs, and in the context of the Socket A platform, that effort made a kind of sense. For the Pentium 4 with an 800MHz bus, though, dual-channel DDR400 is just the right thing to do. The PT880 north bridge contains VIA's first true dual-channel DDR memory controller, and it's apparently a clean-sheet design. One benefit of this approach is that VIA's new chipset is able to run the PCI and AGP busses asynchronously, with clock speeds independent of the front-side bus speed. Overclockers have long enjoyed the ability to lock the PCI bus on Intel chipsets at 33MHz and wail away at the front-side bus at will. PT880 boards should offer the same flexibility.

VIA's marketing name for the PT880's memory controller is DualStream64. The DualStream64 controller has several enhancements over VIA's past memory controllers, including an improved data prefetch protocol, a better memory branch prediction unit with a larger branch table, and "tighter read/write turn around for improved clock timings."

PAT, anyone?

The PT880 north bridge teams up with VIA's now-familiar VT8237 south bridge, replete with Serial ATA RAID and all the rest. Like so:

A block diagram of the PT880 chipset. Source: VIA.

One feature you won't hear much from VIA about, at least connected to the PT880, is quad-band memory support. QBM was supposed to provide a sort of single-DIMM dual-channel memory configuration, and it may yet do so, but VIA's QBM implementation is Not Ready for Prime Time(tm) just yet. For now, VIA wants to focus on dual-channel memory controllers as we have known them, using pairs of conventional DIMMs.

The PT880 north bridge and VT8237 south bridge chips

A heart-to-heart about chip-to-chip
For most intents and purposes, both SiS and VIA are at dead-even feature parity with Intel's 865/875 chipsets, save for a few minor differentiators, like VIA's expanded set of audio options or SiS's Hypers and Stream and such. But those are mostly branding exercises. The biggest difference between these chipsets and Intel's is the link between north bridge and south bridge chips. SiS and VIA have proprietary interconnect solutions—MuTIOL and V-Link Ultra, respectively—that provide 1GB/s of bandwidth between the north bridge and south bridge, which is an appropriate amount given all the I/O capabilities down south. By my count, a pair of SATA ports, a couple of ATA/133 channels, four USB 2.0 hubs, a Fast Ethernet controller, and a PCI bus add up to 911.5MB/s of data, assuming everything involved is going full tilt.

Now, usually not everything is going full tilt, but I'm still puzzled over why Intel's Accelerated Hub Architecture offers only 266MB/s of bandwidth between the north and south bridge chips. Intel sidesteps this problem slightly by routing Gigabit Ethernet over a connection (known as CSA) directly off the north bridge chip. But mobo makers have gotta buy an Intel network chip to use CSA, and CSA is only for Ethernet. In other words, CSA is not the whole answer. At present, VIA and SiS have a leg up here.