We have on the bench the 3800+ model of the Venice Athlon 64, and we've compared it against everything from its direct predecessor, the Athlon 64 "Newcastle" 3800+, to the highfalutin' new dual-core processors from Intel and AMD. We've also attempted to overclock the thing into oblivion. Hop into our gondola and come take a brief tour of Venice with us.

Rev E revs up
One of the first things you need to know about the Venice core is that AMD isn't selling it as anything new or special. In fact, they're not really advertising the changes at all, and we had to goad them into sending one of these puppies out for review. If you go buy a new Athlon 64 with 512K of L2 cache at an online vendor, you may well get the new Venice core, or you might get one of its two predecessors: the "Winchester" core, also built on AMD's 90nm fab process, or the older "Newcastle" core built on a 130nm fab process. These cores sell under some of the same model names, including 3200+, 3500+, and 3800+, depending on clock speed. Fortunately, most of the better online vendors will tell you which version of the K8 core you're buying, so you can pick the right one.

You do want to pick the right one, by the way. Ask AMD, and they will give you a short list of enhancements made to the revision E core that looks like this:

• Support for SSE3 instructions — The Venice core can execute 11 of the 13 instructions that make up SSE3. Pioneered by Intel in its Pentium 4 "Prescott" chips, these 11 instructions are targeted at speeding up certain types of computation. Five of them are aimed at complex math operations like fast Fourier transforms (often used in scientific computing), while another four allow for better data organization in software vertex shader routines for graphics. The handful of others should improve performance in video encoding and speed up conversion of float-point data types to integers. The two SSE3 instructions that the Venice core doesn't support have to do with thread synchronization for Hyper-Threading and simply don't apply here.

• Support for mismatched DIMM sizes per channel — The memory controller built into the Athlon 64 has been tweaked to allow for DIMMs of two different sizes to coexist in a single memory channel. That means it would be possible, in a Socket 939 system with two memory channels, to plug in two pairs of DIMMs that are different sizes without gravely compromising performance.

• Better memory mapping — The rev-E chips can make more efficient use of memory space, although AMD isn't long on details about the changes.

• Improved memory loading — AMD says it's possible with a rev-E chip to populate all of the slots of the motherboard with dual-bank DIMMs without seeing any slowdown.

That's the end of the official list of changes, but I suspect there's more going on here than just that. AMD has also incorporated a number of small changes and fixes into the revision E cores that it doesn't care to talk about. Some of those things are minor modifications deemed too obscure for public consumption, no doubt, but some may be kind of interesting. The Venice core's clock-for-clock performance is up appreciably in certain scenarios, as our benchmarks will show. If you look at this news post from way back in March of 2003, AMD's Kevin McGrath claimed that future Athlon 64 chips would have a number of new features, although he wasn't terribly specific about what would happen when. It's possible that the Venice core is the first to include the enhanced data prefetch function that McGrath described, among others, and some of our benchmark results would appear to support theory.

One thing that we do know about the Venice core is that it's manufactured using AMD's 90nn fab process. Moving from a larger process to a smaller one reduces the overall size of the chip substantially, potentially allowing it to run cooler, require less power, and perhaps operate at higher clock speeds. AMD's 90nm process employs a couple of interesting techniques in order to improve chip properties even further.

The first of these techniques, silicon-on-insulator (SOI) technology, has been used for all Athlon 64 processors. By situating the silicon layer on the chip on top of a film of silicon oxide, an SOI fab process allows for lower transistor capacitance and faster switching speeds.

The second technique, most widely known as strained silicon, is newer. AMD has used it in limited ways in its 130nm process and is now using it more extensively at 90nm. AMD and IBM jointly developed this process, which they call Dual Stress Liner technology. It's so named because the technique allows the firms to compress or stretch the lattice of silicon molecules on a chip, selectively, by placing the silicon on top of one of two layers of silicon nitride. Some types of transistors (PMOS transistors) benefit from the compressive effect, while others (NMOS transistors) benefit from stretch or strain. NMOS transistors, for instance, have lower resistance with strained silicon. AMD has claimed that Dual Stress Liner technology will allow for transistors that switch up to 24% faster at comparable power levels than transistors manufactured conventionally.

Fortunately, the benefits of the SOI and Dual Stress Liner techniques are additive, so they work together to reduce power consumption and increase the switching speed of transistors on the CPU. The end result is chips like our Venice-based Athlon 64 3800+ that should consume less power and, we hope, be willing to run at higher clock speeds, too.