AMD HyperTransport (and Intel QPI Too!)

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AMD HyperTransport (and Intel QPI Too!)

Postposted on Mon Mar 31, 2014 4:30 am

Hey guys, I've been itching to revisit the topic of AMD's (or rather, the HT Consortium's) Hypertransport tech. For the longest time I've come to understand that AMD's CPUs, beginning with their Athlon 64 chips all the way down to today's Visheras, sport 2 x 16-bit HT links, one 16-bit link upstream and one 16-bit link downstream. Is this correct? If you look at the AMD FX Product Page, it says

HyperTransport Technology
* One 16-bit link at up to 5600MT/s
* Up to 8.0GB/s HyperTransport I/O bandwidth; Up to 16GB/s in HyperTransport Generation 3.0 mode
* Up to 37GB/s total delivered processor-to-system bandwidth (HyperTransport bus + memory bus)


Note that the FX supports DDR3-1866 and the page does confirm that total RAM bandwidth is 29.6GB/sec., which is correct. But it also says on the third bullet point above that there's up to 37GB/s worth of off-chip bandwidth, so it means there's around 7.4GB/s worth of HT bandwidth, because DDR3-1866 serves up the remaining 29.6GB/s. If you look at the second bullet point, however, it says there's 8.0GB/s of HT bandwidth, or 16GB/s if you're running in HT3.0 mode. Huh? Aren't these chips supposed to run at the highest HT speeds they can muster and using HT 3.0 when used with a respectable AM3+ motherboard with HT 3.0 support? The first bullet point also says '5600MT/s'. Now how do they do the math? 5600 x 16-bit means there's 11.2GB/s of HT bandwidth, am I correct? Or if we go with the 2 x 16-bit 5600MT/s numbers, there should be 22.4GB/s worth of HT bandwidth, for a total of 52.3GB/s off-chip bandwidth (HT+DDR3). But this is probably wrong.

So, the first bullet point implies 11.2GB/s, the second bullet point says it's either 8.0GB/s or 16GB/s, and the third bullet point suggests that it's 7.4GB/s. WTH, AMD.

Now I'm aware that HT is a packet-based protocol and the data is padded with all sorts of things for control, etc., but Wikipedia also says
With the advent of version 3.1, using full 32-bit links and utilizing the full HyperTransport 3.1 specification's operating frequency, the theoretical transfer rate is 25.6 GB/s (3.2 GHz × 2 transfers per clock cycle × 32 bits per link) per direction, or 51.2 GB/s aggregated throughput


The math is simple enough. If we follow Wikipedia's guidance it means 5600MT/s and a 16-bit (2 x 8-bit) link means 11.2GB/s, aggregate, since I'm assuming the 16-bit HT link includes both up- and down-stream. But is it really just 2 x 8-bit links? I remember my old Athlon 64 X2 PC's BIOS having an option where in you can change the HT link from 2 x 16-bit or 2 x 8-bit. AMD must be nuts to cut HT bandwidth from a 2-CPU to an 8-core CPU.

And as for QPI, Intel practically doesn't even want people to bother with QPI speeds and whatnots. ARK mentions QPI (or DMI) speeds but that's it. No bandwidth claims, just GT/s numbers.
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 9:46 am

Ok, I found a great article over at Hardware Secrets. I guess it confirms my stock knowledge about HT, and I guess AMD's numbers are messed up. Here, check it out and teach yourselves everything you wanna know about HT.

http://www.hardwaresecrets.com/article/ ... t-Bus/19/1
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 1:41 pm

You needn't look far for some QPI info - this link is at the bottom of the page you linked:

http://www.hardwaresecrets.com/article/Everything-You-Need-to-Know-About-The-QuickPath-Interconnect-QPI/610

Also, it doesn't look like Intel is very secretive about it.

http://www.intel.com/content/www/us/en/io/quickpath-technology/quick-path-interconnect-introduction-paper.html

Which of today's processors use QPI anyway? MP Xeons? i5-4440 and i5-4440S, as Ark claims?
Last edited by Wirko on Sat Apr 05, 2014 2:03 pm, edited 1 time in total.
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 2:02 pm

Wirko wrote:Which of today's processors use QPI anyway? MP Xeons?

It is also used to connect single-socket CPUs to the I/O hub (not just for inter-socket links in MP configuration). IOW it is pretty much completely analogous to HyperTransport.
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 6:11 pm

^ I thought they replaced QPI with DMI for the single socket chips.
ARK for the E5-1650v2 specifies "0 GT/s" for the QPI speed, with "0" QPI links available.

http://ark.intel.com/products/75780/Int ... e-3_50-GHz
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 7:01 pm

jihadjoe wrote:^ I thought they replaced QPI with DMI for the single socket chips.
ARK for the E5-1650v2 specifies "0 GT/s" for the QPI speed, with "0" QPI links available.

http://ark.intel.com/products/75780/Int ... e-3_50-GHz

Ahh, you are in fact correct, my bad. On current single-socket chips it is used internally to connect the cores to the memory controller, but generally is not exposed outside the chip package.
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 8:08 pm

From what I've read QPI isn't even used to do that anymore since Sandy Bridge.
Since the memory controller is now completely on-die as opposed to being an MCM module in Nehalem, the QPI link between the CPU and MC is completely gone, replaced instead by the new internal ring bus (which is arguably QPI-like, but not quite QPI).

David Kanter's Sandry Bridge architecture evaluation says (underline mine):

As Moore’s Law has given more transistors with each generation, the level of achievable integration on microprocessors has steadily climbed. Intel came rather late to the integration game – it wasn’t until the 45nm Nehalem in 2008 that the memory controllers and coherent interconnects moved into the CPU silicon. However, as befitting the company that lives by Moore’s Law, they have come to the integration game with a vengeance. The 32nm client versions of Westmere packaged the microprocessor with a companion die that included graphics and a memory controller and other features; the two chips were connected via QPI. Sandy Bridge takes this to the logical conclusion and integrates almost everything found in the previous generation into a single 32nm die and eliminates the QPI link.


Intel's own Oded Lempel illustrates this in his Sandy Bridge Presentation @ HC.org.
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 8:20 pm

jihadjoe wrote:Since the memory controller is now completely on-die as opposed to being an MCM module in Nehalem, the QPI link between the CPU and MC is completely gone, replaced instead by the new internal ring bus (which is arguably QPI-like, but not quite QPI).

The Kanter article you linked actually says "The protocol is an enhanced version of QPI with some specific additional features." It sounds like it is essentially an evolution of QPI, modified for on-die use.
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Re: AMD HyperTransport (and Intel QPI Too!)

Postposted on Sat Apr 05, 2014 8:37 pm

Yep. Which is why I said the ring bus is QPI-like. It builds on the technologies of QPI, but likely eliminates several protocol layers (basically simplifies the routing layer, since all addresses will be internal to the SOI, and eliminates the transport layer), and expands the width and speed of the interconnect (ring bus transfers 256 bits per cycle, vs QPI which transfers 80 bits over 2 clocks with a 64-bit payload) hence it's "not quite QPI".

Edit: This page has a few architecture diagrams for Sandy Bridge-EP. You can see how the ring bus connects the QPI controller, Memory Controller and LLC to the cores. It's a pretty clear illustration that the ring bus is a separate entity from QPI and functions at a level much closer to the CPU itself.
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