VHDL?

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VHDL?

Postposted on Thu Jul 02, 2009 7:59 am

And now for something completely different...

It appears that I'll soon be getting another hat at work, to add to add to the half-dozen or so (firmware developer, IT support, sysadmin, circuit-level hardware troubleshooting, marketing support, etc.) I already need to wear on a regular basis. This one is going to require me to do some FPGA design work!

Can someone point me at some good online resources for getting up to speed with VHDL? Employer will probably send me to some sort of training class, but money is a little tight so I suspect they may try to cut corners on that, and I'd like to get a jump start on it regardless.
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Re: VHDL?

Postposted on Thu Jul 02, 2009 9:31 am

just brew it! wrote:It appears that I'll soon be getting another hat at work, to add to add to the half-dozen or so (firmware developer, IT support, sysadmin, circuit-level hardware troubleshooting, marketing support, etc.) I already need to wear on a regular basis. This one is going to require me to do some FPGA design work!

I can see why you're "Somewhere, having a beer."
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Re: VHDL?

Postposted on Thu Jul 02, 2009 9:38 am

Xlinx ISE and the related documentation should help, but "verilog tutorial" also comes up with some good picks. It all depends on how you like to study.

In general, VHDL and FPGA designing and debugging is pretty unpleasant if you have used to C++ and MSVS IDEs and development practices. Coding seems to be quite similar to C++/C except all that concurrency, cycles and register stuff, that is really hard to grasp.
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Re: VHDL?

Postposted on Thu Jul 02, 2009 9:52 am

bdwilcox wrote:I can see why you're "Somewhere, having a beer."

Hey, versatility is one of the best defenses in a crappy job market. While it does sometimes make for days which consist of nothing but interruptions, I welcome the experience. It makes me more valuable to my employer (so less likely to be one of the first to be let go if there's a layoff), and opens up additional possibilities should I need to find another job.

Madman wrote:Xlinx ISE and the related documentation should help, but "verilog tutorial" also comes up with some good picks. It all depends on how you like to study.

In general, VHDL and FPGA designing and debugging is pretty unpleasant if you have used to C++ and MSVS IDEs and development practices. Coding seems to be quite similar to C++/C except all that concurrency, cycles and register stuff, that is really hard to grasp.

Thanks for the tips, I will check them out.

While I've done a fair bit of MSVC++ (yes, yet another hat... though mostly at previous jobs, not this one), I've also done a lot of embedded code, multi-threaded code, and assembly langauge. So I imagine the transition to the hardware level will be less painful than it would be for someone who has spent most of their life building GUI apps on Windows. :wink:
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Re: VHDL?

Postposted on Thu Jul 02, 2009 10:36 am

My own experience and Wikipedia suggest that VHDL is closer to the Ada/Pascal lineage, I am sure JBI can handle that. Verilog is kind of an odd animal because they are not exactly standard VHDL (think of it as like Javascript has only very few things similar to Java? may be not quite, but you get the idea), so we kind of need to know what compiler/simulation package will be used.
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Re: VHDL?

Postposted on Thu Jul 02, 2009 11:00 am

All I know about the platform so far is that we are using Altera FPGAs.
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Re: VHDL?

Postposted on Thu Jul 02, 2009 11:17 am

just brew it! wrote:
bdwilcox wrote:I can see why you're "Somewhere, having a beer."

Hey, versatility is one of the best defenses in a crappy job market. While it does sometimes make for days which consist of nothing but interruptions, I welcome the experience. It makes me more valuable to my employer (so less likely to be one of the first to be let go if there's a layoff), and opens up additional possibilities should I need to find another job.


Surely it should be 'Somewhere else, having another beer' by now? Sadly I'd be about as much help as a chocolate fireguard on this one.
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Re: VHDL?

Postposted on Thu Jul 02, 2009 11:53 am

My recommendation would be to pick up "VHDL" by Douglas Perry (ISBN 0-07-049436-3). It is a fairly thorough that takes you from an introduction to VHDL terms through behavioral modeling, data types and attributes, to Synthesis and RTL simulation. Personally, I prefer Verilog, probably because I learned it first and it is very "C-ish". I started an attempt to learn VHDL to the same level, but haven't gotten that far. I don't have any job requirement to learn it and since I can do Verilog I can do what I need with the FPGA boards I have.

The hardest thing about learning Verilog/VHDL (at least for most people) is the parallelism. Remember that for a given clock cycle, every statement that is going to execute will execute effectively at the same time even though they may look sequential in the code. If you are comfortable with multithreaded programming with large amounts of data shared between the threads, then you will have a definite head start.

Have fun.

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Re: VHDL?

Postposted on Thu Jul 02, 2009 12:46 pm

Richie_G wrote:Surely it should be 'Somewhere else, having another beer' by now?

It pays well, and for the time being defense is more stable than the telecom or financial industries (which are the other two main sources of high tech jobs in the Chicago area). The level of chaos these past few months is starting to get to me though... next week I get to go to Tampa to wear my marketing hat for a couple of days (just found out about this on Monday). :roll:
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Re: VHDL?

Postposted on Thu Jul 02, 2009 10:19 pm

Personally, I've had more success trying to avoid seeing VHDL as I would a programming language and think in terms of hardware (register transfers, timers and such), particularly because of the nature of the execution (everything happening at once, etc.). Some people simplify things by implementing hardware in the form of state machines, however I'm not sure if there would be a performance trade-off by doing this.
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Re: VHDL?

Postposted on Thu Jul 02, 2009 10:37 pm

I learned some VHDL in college and it was all done by reading a book and trying stuff out. I dunno, i think it just takes time to get used to. Here are some online things that might help.

http://equipe.nce.ufrj.br/gabriel/vhdlfpga.html
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Re: VHDL?

Postposted on Thu Jul 02, 2009 10:53 pm

DancinJack wrote:I learned some VHDL in college and it was all done by reading a book and trying stuff out. I dunno, i think it just takes time to get used to. Here are some online things that might help.

http://equipe.nce.ufrj.br/gabriel/vhdlfpga.html

I seem to remember VHDL Cookbook.
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Re: VHDL?

Postposted on Thu Jul 02, 2009 11:31 pm

Wajo wrote:Personally, I've had more success trying to avoid seeing VHDL as I would a programming language and think in terms of hardware (register transfers, timers and such), particularly because of the nature of the execution (everything happening at once, etc.). Some people simplify things by implementing hardware in the form of state machines, however I'm not sure if there would be a performance trade-off by doing this.

The application at hand is (primarily) concerned with video processing. Sort of like a custom GPU, with multiple pipelines processing groups of pixels. So I imagine state machines will likely be the way to go...
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Re: VHDL?

Postposted on Fri Jul 03, 2009 12:21 am

Yeah, think hardware, not software. If you've programmed low-level before then it shouldn't take too long to get up to speed; but still, it's not programming, it's defining hardware. Depending on how demanding your application is, you'll also have to define timing constraints and possibly location constraints... I don't know how to do that in Altera-land but no doubt it's in their tutorials.

If you're making lots of identical processing blocks, then VHDL has some useful features, like generate and for loops.
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Re: VHDL?

Postposted on Tue Jun 15, 2010 11:11 pm

Thread necro time!

It took a little longer than expected for the project I was going to need VHDL for to ramp up, so I had more or less dropped it after reading about half of a VHDL textbook last summer. Suddenly it is everyone's top priority again (including mine).

I just took a 1-day introductory VHDL course at the local Altera offices today, and I have to say that helped a lot. The instructor was very good; things just started to "click", and a lot of the stuff I wasn't quite understanding from the textbook make sense now (I asked a lot of questions, and the instructor was able to answer every one of them).

I've gone from being fairly clueless and intimidated, to "hey with a little more practice I can do this".

Now to start designing that custom video processing engine they wanted a month ago... :lol:
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Re: VHDL?

Postposted on Wed Jun 16, 2010 12:37 am

what is truly awesome about this - is that they've gone in house to develop something when their resource (JBI) obviously couldn't do it, but they knew he eventually could do it. that's a great employer.

I've hacked in some VHDL before. It was truly messy :) .. if you want to relate it to programming, then it is the same as far as typing into a editor and then compiling and loading like any embedded programming.

however, the debugging you'll want to do (unless you trust the simulator) will be using built in Quartus live inspection tools (can't remember their names) or just straight up debug signals ported out the real world.
What I found almost impossible to do without was a multi-channel digital analyser. I bought a LogicPort 34-channel USB to a PC front-end thingy. It was US$600ish .. there might be better options out their right now.
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Re: VHDL?

Postposted on Wed Jun 16, 2010 10:02 am

balzi wrote:what is truly awesome about this - is that they've gone in house to develop something when their resource (JBI) obviously couldn't do it, but they knew he eventually could do it. that's a great employer.

Heh... if you'd witnessed first-hand the series of events which led to the creation of this project (and me being asked to do some of the FPGA work) you probably wouldn't think so! :lol:

But, at the end of the day I still get to learn something new and interesting so overall I'd say it is a net positive.
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Re: VHDL?

Postposted on Tue Jun 22, 2010 9:41 pm

just brew it! wrote:Heh... if you'd witnessed first-hand the series of events which led to the creation of this project (and me being asked to do some of the FPGA work) you probably wouldn't think so! :lol:

But, at the end of the day I still get to learn something new and interesting so overall I'd say it is a net positive.

:roll: hmm, bit a incompetence mixed with enthusiam? or did they try some contractors and get burned?

did you get yourself a USB digital analyser? There's better ones out I expect, but I'm happy with the sucker I got here http://www.pctestinstruments.com/.
My favourite part is the incredibly flexible triggering to capture.. oscilliscopes are great, but this lets you do so much more when messing with digital signals only.
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Re: VHDL?

Postposted on Wed Jun 23, 2010 7:43 am

balzi wrote:did you get yourself a USB digital analyser? There's better ones out I expect, but I'm happy with the sucker I got here http://www.pctestinstruments.com/.
My favourite part is the incredibly flexible triggering to capture.. oscilliscopes are great, but this lets you do so much more when messing with digital signals only.

We've already got some pretty good tools at the office for stuff like that, but this one looks like something I might want for home (as noted in another thread, I'm also teaching myself how to do microcontroller development).
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Re: VHDL?

Postposted on Fri Jun 25, 2010 2:35 am

I've written a few very basic scripts to help manage a project similar to yours. I would suggest spending some time with Perl or Python and writing plenty of scripts to create macros, substitute values/variables, and to verify your output to make sure that your logic doesn't have any obvious errors with your buses connecting. You can certainly buy some of that stuff but if you are under budget constraints its pretty easy to write yourself.
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Re: VHDL?

Postposted on Fri Jun 25, 2010 9:15 am

Yup, we already use Python extensively to drive our software tests, so extending that to firmware tests is not a huge leap.
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Re: VHDL?

Postposted on Sun Jun 27, 2010 6:50 pm

just brew it! wrote:
Wajo wrote:Personally, I've had more success trying to avoid seeing VHDL as I would a programming language and think in terms of hardware (register transfers, timers and such), particularly because of the nature of the execution (everything happening at once, etc.). Some people simplify things by implementing hardware in the form of state machines, however I'm not sure if there would be a performance trade-off by doing this.

The application at hand is (primarily) concerned with video processing. Sort of like a custom GPU, with multiple pipelines processing groups of pixels. So I imagine state machines will likely be the way to go...


Reading this post makes me think of the Open Graphics Project which is an FPGA-based prototyping platform that can be made into a graphics card. I'm not sure if there are any parallels with what you are doing but they sound similar.

A recent interview with project members
http://opengraphics.org/
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Re: VHDL?

Postposted on Sun Jun 27, 2010 8:15 pm

All I know is switching from VHDL coding to C# to assembly and back really makes my head hurt. Something about the different mentalities makes throwing VHDL into the mix an almost impossible task for me. One or the other at a time, not both. Oh, lets try to toss a little board layout in there too. Oil and water...

Working with FPGAs is simply far too much fun, as those things can scream out some impressive number-crunches. Humongous FFTs far faster than a PC could ever hope, video processing, encrypting, software defined radios... However, I have found that because of that mix of different sides of the brain mentioned above needed to write excellent VHDLwhile performing other tasks, I had to divorce myself from VHDL and let the guys who specialize in that stay with it. Much more efficient in the end.

The book mentioned above is an excellent one, I use it as a reference a lot, but hopefully not for a while again.

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Re: VHDL?

Postposted on Sun Jun 27, 2010 9:57 pm

liquidsquid wrote:All I know is switching from VHDL coding to C# to assembly and back really makes my head hurt.

Heh. I already switch around a lot betwen C/C++, Python, and bash shell scripting. Sometimes even all in the same day. Hopefully VHDL won't push me past the tipping point! :lol:
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Re: VHDL?

Postposted on Mon Jun 28, 2010 12:19 am

liquidsquid wrote:All I know is switching from VHDL coding to C# to assembly and back really makes my head hurt. Something about the different mentalities makes throwing VHDL into the mix an almost impossible task for me. One or the other at a time, not both. Oh, lets try to toss a little board layout in there too. Oil and water...

Working with FPGAs is simply far too much fun, as those things can scream out some impressive number-crunches. Humongous FFTs far faster than a PC could ever hope, video processing, encrypting, software defined radios... However, I have found that because of that mix of different sides of the brain mentioned above needed to write excellent VHDLwhile performing other tasks, I had to divorce myself from VHDL and let the guys who specialize in that stay with it. Much more efficient in the end.

The book mentioned above is an excellent one, I use it as a reference a lot, but hopefully not for a while again.

-Mark


I sort of found assembly, FPGA devel (albeit a limited scope) and uC devel to be in a similar vein. perhaps the brain pathways do need to be opened in a different way.
I definitely agree with your call that having someone who specialises in one area should be better.
But the most effective person I've found is someone who has:
1. Got a specialised-level grasp of their area of devel.
2. An experienced awareness of other areas - helps them know when they shouldn't be doing something, because you know, Bill over there could get this done much cheaper, cleaner, etc with his HW modules. blah blah
3. Can see the big picture of a project and work to that with a flexible mind, rather than just crunch/grind out something confirming to a (possibly) inadequate spec.

good luck JBI. I stand by my thought that you have a good employer, but maybe only because I envy someone who can get their hands dirty in Bash, Perl, Python and FPGA.
I like my mix of Linux Embedded (out of my league somewhat), microController PIC, simple circuit design, Perl, bash, PHP (again simple only).. but the grass is always greener right?!?
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Re: VHDL?

Postposted on Wed Apr 11, 2012 8:02 pm

Massive thread necro! :lol: (But quite appropriate, given that the project which originally spawned this thread was put on extended hold, then brought back from the dead recently...)

So I'm finally compiling my code to be loaded into real FPGA hardware instead of just running it in a software simulator. The tool (Altera Quartus II suite) has been frustrating; very long compile times, and not infrequent crashes. Tomorrow my office mate is going to be the guinea pig for the latest Quartus II service pack, to see if it is an improvement.

Moving from the simulation world to running on the actual hardware has been interesting to say the least. There are some VHDL constructs which simulate just fine, but don't work well (or seriously hinder debugging) in real hardware. Reliably interfacing to external DDR3 RAM (we need external RAM since there isn't enough internal RAM in the FPGA to do what we need) has also been a major PITA.

All things considered, it has been interesting... in both the good and bad senses of the word. Finally getting an output image to a DVI display a couple of days ago was a pretty major thrill.

Yes, it's kind of like assembly language... but a couple of levels below even that. Instead of having to visualize data moving around between CPU registers and RAM locations, you actually need to visualize it moving along wires between different logic blocks... bare metal indeed! :lol:

We're nowhere near done yet... but I finally feel like I've come up the learning curve and say that I'm competent in VHDL.
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Re: VHDL?

Postposted on Wed Apr 11, 2012 8:36 pm

Are you using a 3rd party IP block for the memory controller, or are you jumping in the deep end and rolling your own?

There is a huge difference in simulation and the physical world. On the face of it, it would appear that there is much more to VHDL that will not synthesize that in Verilog, but that may just be my familiarity with Verilog. I've been through VHDL classes and wasn't really impressed.

Congrats on making progress though. FPGA stuff is something I have tinkered with as a hobby/play thing until just recently. Now I support an FPGA based hybrid co-processor architecture and system. Major change in jobs and focus, but I'm looking forward to the challenge.

As someone mentioned earlier in the thread, you have to think of things in terms of wires, gates, and flip-flops. Programming constructs that don't line up don't synthesize well. Of course I still get told be EE friends that I write Verilog like a software guy. :wink:

Have fun and enjoy the learning process.

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Re: VHDL?

Postposted on Wed Apr 11, 2012 10:11 pm

just brew it! wrote:you actually need to visualize it moving along wires between different logic blocks... bare metal indeed! :lol:

Sometimes you do have to do that with a scope and look at signal waveform, literally.
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Re: VHDL?

Postposted on Thu Apr 12, 2012 6:48 am

SecretSquirrel wrote:Are you using a 3rd party IP block for the memory controller, or are you jumping in the deep end and rolling your own?

We're currently using Altera's DDR3 controller IP. It's a PITA. We may eventually end up keeping just their PHY and re-rolling the rest of it ourselves, but we've got bigger fish to fry right now.

SecretSquirrel wrote:There is a huge difference in simulation and the physical world. On the face of it, it would appear that there is much more to VHDL that will not synthesize that in Verilog, but that may just be my familiarity with Verilog. I've been through VHDL classes and wasn't really impressed.

Most of my newbie type mistakes were more along the lines of stuff that would still synthesize, but made the design difficult to debug once it was on the real hardware. Well, and then there was the hand-coded dual-port RAM block which didn't map cleanly to the FPGA's canned RAM arrays, causing the synthesis tool to build the entire memory array out of logic gates; this caused compile times to increase exponentially (18 hours)! :o

Edit: I also didn't realize until a month or so ago (when I started trying to test on "real" hardware) that creating tri-state busses internal to your design (as opposed to tri-state external interfaces) is frowned upon. I ended up ripping all of the tri-state signals out of my design and replacing them with muxes.

SecretSquirrel wrote:Congrats on making progress though. FPGA stuff is something I have tinkered with as a hobby/play thing until just recently. Now I support an FPGA based hybrid co-processor architecture and system. Major change in jobs and focus, but I'm looking forward to the challenge.

Thanks. There's a soft MIPS core processor in this design too (compiled into the FPGA). Someone else has been working on that piece, but once my block is fully debugged I will need to interface it to the processor.

SecretSquirrel wrote:As someone mentioned earlier in the thread, you have to think of things in terms of wires, gates, and flip-flops. Programming constructs that don't line up don't synthesize well. Of course I still get told be EE friends that I write Verilog like a software guy. :wink:

Oh, I'm sure I write VHDL like a software guy too! It looks just enough like C code to get you in trouble... :lol:

Edit: The whole parallel vs. sequential thing is a major brain-bender. And then there's the whole business of making sure you don't create logic blocks that force the synthesis tool to create transparent latches behind your back...

Flying Fox wrote:
just brew it! wrote:you actually need to visualize it moving along wires between different logic blocks... bare metal indeed! :lol:

Sometimes you do have to do that with a scope and look at signal waveform, literally.

During debugging you need to look at signals internal to the chip that don't make it out to the external pins. The tools allow you to compile a "soft" logic analyzer right into the FPGA, which then talks to your workstation to display the waveforms. The downside is adding or moving "probes" takes half an hour because you need to recompile the entire design! :-?
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Re: VHDL?

Postposted on Thu Apr 12, 2012 8:45 pm

just brew it! wrote:
SecretSquirrel wrote:Are you using a 3rd party IP block for the memory controller, or are you jumping in the deep end and rolling your own?

We're currently using Altera's DDR3 controller IP. It's a PITA. We may eventually end up keeping just their PHY and re-rolling the rest of it ourselves, but we've got bigger fish to fry right now.

SecretSquirrel wrote:There is a huge difference in simulation and the physical world. On the face of it, it would appear that there is much more to VHDL that will not synthesize that in Verilog, but that may just be my familiarity with Verilog. I've been through VHDL classes and wasn't really impressed.

Most of my newbie type mistakes were more along the lines of stuff that would still synthesize, but made the design difficult to debug once it was on the real hardware. Well, and then there was the hand-coded dual-port RAM block which didn't map cleanly to the FPGA's canned RAM arrays, causing the synthesis tool to build the entire memory array out of logic gates; this caused compile times to increase exponentially (18 hours)! :o


Yeah. I've kind of learned that I'm not good enough to make the compiler properly infer chip resources from my code. In the end I usually just instantiate the primitive to ensure that it does the right thing. Now I'm sure some guru will argue that this causes the design to by un-portable, but in my limited experience, even a design where stuff is inferred only really works on one, or a very small set of chips. Outside that, the compiler goes and does the stupid thing.

I have learned that to get a design to synthesize very efficiently requires very good understanding of the FPGA resources, logic element construction, and routing resources. All stuff you don't have to have in simulation.

just brew it! wrote:Edit: I also didn't realize until a month or so ago (when I started trying to test on "real" hardware) that creating tri-state busses internal to your design (as opposed to tri-state external interfaces) is frowned upon. I ended up ripping all of the tri-state signals out of my design and replacing them with muxes.


I tried to do the same thing at first, mainly because putting all the muxes in seemed like such a waste of resources. Luckily I had a mentor who made me see the light rather quickly. I still have a hard time with multi-device bi-direction busses though. My habit is to think about it in the physical hardware sense, not in the logic hardware sense.

just brew it! wrote:
SecretSquirrel wrote:Congrats on making progress though. FPGA stuff is something I have tinkered with as a hobby/play thing until just recently. Now I support an FPGA based hybrid co-processor architecture and system. Major change in jobs and focus, but I'm looking forward to the challenge.

Thanks. There's a soft MIPS core processor in this design too (compiled into the FPGA). Someone else has been working on that piece, but once my block is fully debugged I will need to interface it to the processor.

SecretSquirrel wrote:As someone mentioned earlier in the thread, you have to think of things in terms of wires, gates, and flip-flops. Programming constructs that don't line up don't synthesize well. Of course I still get told be EE friends that I write Verilog like a software guy. :wink:

Oh, I'm sure I write VHDL like a software guy too! It looks just enough like C code to get you in trouble... :lol:

Edit: The whole parallel vs. sequential thing is a major brain-bender. And then there's the whole business of making sure you don't create logic blocks that force the synthesis tool to create transparent latches behind your back...

Flying Fox wrote:
just brew it! wrote:you actually need to visualize it moving along wires between different logic blocks... bare metal indeed! :lol:

Sometimes you do have to do that with a scope and look at signal waveform, literally.

During debugging you need to look at signals internal to the chip that don't make it out to the external pins. The tools allow you to compile a "soft" logic analyzer right into the FPGA, which then talks to your workstation to display the waveforms. The downside is adding or moving "probes" takes half an hour because you need to recompile the entire design! :-?


What is it called in the Altera world? Xilinix calls theirs ChipScope. Very handy. :)

I've been meaning to get an Altera board to play with. I've worked with Xilinx and Lattice, but not Altera.

--SS
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