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Well first off can we please avoid any trolling and flame wars.

Now onto the post. So it's nice that Glo Fo/Samsungs 14nm fab is up and running as is TSMC 16nm finfet. From all the vid card reviews lately we have seen that GloFo silicon is being fed much more voltage than TSMC silicon, plus it's running at way lower clocks.

Now I have never seen the inside of a silicon crystal fab or how many crystal fabs there are or different types of doping. Also I have never been in a lithography fab.

I'm curious from a strictly science point of view why there is such a difference between the 2 new chips??

From a very basic logical view if all things were considered equal 14nm and 16nm should behave/perform almost identically, but from practice they don't. Others have mentioned that the iphones built on samsung vs. TSMC silicon also have noticeable differences.

So what can be the cause(s).

1. Cooling can be an obvious one, so we'll leave it out.

2. Silicon. Who manufactures the silicon come (does each fab grow & dope their own crystals depending on requirements? And how/why does the doping vary depending on application? And is that information available? Do the fabs buy silicon crystals from a 3rd party?

3. Is AMD putting too much of a safety buffer on over volting - could the GloFO silicon run well on 20% less voltage?

4. Lithography - I don't know who actually constructs these machines, and if GloFO and TSMC have machines that are similar or different, but maybe even from the same manufacturer??
Can the etching done to the silicon by lithography actually make such a big difference in clocks, voltage requirements and power consumption?? How/why?

5. Leakage??

6. The architecture itself?

7. Other? Type of lithography and/or process??

I find this stuff very intriguing, but I think these questions are more suited to Dave Kanter or someone in that industry.

2) Intel buys silicon wafers from third parties. (Slide 4) As far as I know no fab actually makes its own silicon ingots, though I think I recall hearing about one that did buy ingots and sliced the wafers themselves? Maybe I'm just thinking of some NAND companies that bought NAND wafers whole and sliced those up in-house. Either way I imagine Intel uses specific supplier(s) instead of buying off the general wafer market.

4) Applied Materials produces the machines used in practically all global fabs

7) It's a core difference between the fabrication processes each fab uses. Even if the process node was an identical 14nm between two different company's fabs, they would still have different internal sizes on the actual logic components they are fabricating. There's an insane number of ways to measure transistors and gates beyond the process node. There are internal measurements like height and width of a gate itself, the features inside a single gate, pitch between fins, and then the process size of the interconnects between them just for starters... this PDF has pretty much everything on it

Among other things these differences in fixed size constraints are why an identical core design has to be taped out individually per every fab that plans to make it. TSMC and Glofo have difference fixed sizes on the internal logic, and this in turn affects the shape of the logic layout for the mask. Regardless of the process priority/type (low power, high clocks, or logic desnsity) it doesn't matter, the bluepint/mask of the same core is going to tangibly even visually differ. if the mask bluepint differs then obviously the final resulting silicon will differ too and that plays into all the rest of the factors. Apple's A9 fabbed at Samsung and TSMC was a neat example of this. http://www.chipworks.com/sites/default/ ... image6.jpg

Edit: Fixed a typo

4) I believe you mean Applied materials, Novellus is another manufacturer of the toolsets that are used to handle and process the wafers and ASML (advanced semiconductor materials) that is the company that dominates the entire industry. They make virtually every photolithography toolset in the world. I dont believe they have any real competition. Not any major, anyway.

7) Yes. In addition to the differences they are virtually identical! Samsung and Global use the term 14nm. TSMC uses 16nm. A difference of nomenclature. The designers have a little flexibility when designing a transistor. Even though two race cars may use the same engine, one team tweaks it differently so wins the race. When designing a wafer the same ideas apply. A little less here a little more there and you wind up with a recipe that goes into intellectual property. I dont know specifics but go to {techdesignforums.com/practice/guides/14nm-16nm-processes/} and they will have more specifics (new member, cant post links yet).
When I find out more about why,since I have been in the inside of a fab, I will post it here.

(edit: add info)

Well some feedback at least.

Is there specific tests that can done for putting a number to leakage?

Different fabs run different process'.

TSMC is very good at what they do, GF, a bit less so.

GF was partnered with IBM to develop their process but IBM has been going through some big changes that screwed that up.

GF's initial 14nm PDK sucked ass. They have since partnered with Samsung to be their second source and thus share their process.

On a physics level, it is hard to say which is better without looking at their respective device models and sample layout to see what kind of density can be achieved.

Outside of place and route blocks, high speed custom layout can actually require more space than the equivalent at 28nm.

A big thing that everyone deals with is that although the finfet transistors are great, the metals they connect with are very weak. EM/IR issues are a huge deal as are the parasitic capacitance caused by wires that are close together. That requires post layout parasitic extraction and back annotated simulation which takes a lot of time. It takes so much time that the engineers have to start skipping certain simulations so nothing is ever 100% verified.

It's like sausage.

I find it amazing how much behind the scenes work goes on that most people never heard about, but is so critical in making a good modern working piece of silicon.

Be nice if Kanter could chime in.

Subscribed.

I don't think that Samsung's process is significantly slower than TSMC's. I'd be surprised if it was more than 10% difference. Samsung's is a bit denser, which we know from comparing the A9 on 14nm and the A9 on 16nm.

Nvidia's has a lot more money to invest, and they are solely focused on PC gaming (i.e., DX11). AMD has less money and cares a lot about consoles and DX12/Vulkan, so they are optimizing more for that. As a result of the lower investment at AMD, the shaders are pretty similar for GCN generations. OTOH, NV has really changed architecture a lot, which should improve perf and power.

Even if you assume 10-20% frequency advantage for process (and I believe its more like 0-10% myself), you still cannot get around the fact that Nvidia's clocks are almost 50% higher. So there's a lot of architectural and circuit optimization that is playing a role there.

Also, if you look at AMD's claims, they are stating upto 2.8X better perf/watt. I think that the sweet spot they designed for was really Polaris 11, which probably sees the biggest boost. It could be that Polaris 10 doesn't improve quite as much.

David

PS: Now that I responded, you all have to help me figure out how to get my damn system to wake up properly in Win10, see this thread: viewtopic.php?f=29&t=118272

Speed relies more on design than process.

AMD was making 5GHz CPUs on a 28nm process, I think Intel has gotten to 4.1GHz on 14nm. Different types of circuits can run a lot faster than that, it's just difficult to make a whole chip run fast. Also a fast clock doesn't mean superior performance in every case.

I have heard that Nvidia uses a ton of place and route. The way that works is their logic designers write Verilog code which describes the circuit and then a software P&R tool generates layout by placing standard cells from a library and routing the power and signal connections. The quality of that layout depends on a lot of factors. The quality of the P&R cell library is a big deal. The way the Verilog is written is a big deal. The way the P&R tool works is a big deal.

Some times a circuit will be laid out with P&R and then tweaked by hand. I don't know how much Nvidia does that but their results suggest they spend some time ensuring that they can hit high clock speeds.

Finally, it gets back to the wires. Higher clock speeds make a chip use more power and when you use more power you can exceed the EM limit of the chip which will reduce the projected life span of the chip. If you can add enough wire to keep the EM results well under the limit you can run faster without causing problems but more wire makes more capacitance which is a problem for high clock speeds.

It's just a delicate balance of optimizations.

One more thing, the fin fet process has almost eliminated the planar transistor leakage problem so the chips can run higher voltage if they want to without losing it as leakage current. That voltage is going to get lower as oxide thicknesses get thinner at smaller processes but putting a lot of voltage on a fin fet chip might be more likely to cause an EM problem in the wires than smoke a transistor.

Interesting. Thanks for the feedback.