Personal computing discussed
Moderators: renee, Flying Fox, Thresher
EV42TMAN wrote:anyone that says you can get away with high end non ECC memory doesn't directly work with databases
Evan wrote:Cool, I'll place the order. I'm glad to hear that this specific setup will have real protection. I was concerned that there was some catch and the full benefits wouldn't be realized on this system (because it's essentaillly an enthusiast machine with a quasi-server single-socket motherboard, and doesn't have true server parts throughout).if you're using the system for something serious like a database, I'd say go for the ECC.
derFunkenstein wrote:Oh right, it's a pre-Nehalem Intel. How quickly I forget.The memory controller is what determines ECC support, rather than the CPU in this case (since the memory controller isn't on the CPU), so you should be OK to do that without a CPU swap.
derFunkenstein wrote:As to what you gain, I dunno. It seems to me that ECC isn't worth the cost simply because if you're getting data corruption errors due to memory, you just have bad memory in the first place and replacing it with cheaper unbuffered non-ECC should fix it just as well.
derFunkenstein wrote:The second C stands for Code, I thought. Error Correcting Code.
derFunkenstein wrote:EV42TMAN wrote:anyone that says you can get away with high end non ECC memory doesn't directly work with databases
That's not true. You know, just based on what I do and what I just said.
I just don't wield my job like a hammer and slap everyone with it like it's my dick. Mostly because I don't want to be bothered.
The RAM Guy wrote:Q: Come on... cosmic rays? Really, how often does this occur?
A: The Ram Guy consulted with some experts on this one. Basically, it's a statistics problem. But, when you do the math, a soft error is likely to occur in a system with 256 Mbytes of memory about every 750 hours! And, the more memory you have, the more frequently soft errors will occur.
Ryu Connor wrote:This old FAQ from Corsiar makes some claims regarding the average statistics of a soft error:The RAM Guy wrote:Q: Come on... cosmic rays? Really, how often does this occur?
A: The Ram Guy consulted with some experts on this one. Basically, it's a statistics problem. But, when you do the math, a soft error is likely to occur in a system with 256 Mbytes of memory about every 750 hours! And, the more memory you have, the more frequently soft errors will occur.
Those numbers seem a tad high. One would think my 24GB system would be falling over rapidly with values as reported.
Ryu Connor wrote:This old FAQ from Corsiar makes some claims regarding the average statistics of a soft error:The RAM Guy wrote:Q: Come on... cosmic rays? Really, how often does this occur?
A: The Ram Guy consulted with some experts on this one. Basically, it's a statistics problem. But, when you do the math, a soft error is likely to occur in a system with 256 Mbytes of memory about every 750 hours! And, the more memory you have, the more frequently soft errors will occur.
Those numbers seem a tad high. One would think my 24GB system would be falling over rapidly with values as reported.
just brew it! wrote:A and B give people who worry about system uptime nightmares; E is the bugaboo for people who worry about data integrity.
Captain Ned wrote:How deep are the tunnels at FermiLab, and how deep do they have to be to block cosmic rays (mainly highly-energetic protons)?
Krogoth wrote:There's no guarantee that my research is flawless, but the motherboard manual (and the page I linked to in the OP) claim that ECC is supported. Are you seeing something I'm missing?For OP, you need to get a X38/X48 board in order to get ECC support for your Core 2 Quad. FYI, not all X38/X48 boards have ECC support, so research carefully on the motherboard features.
wibeasley wrote:There's no guarantee that my research is flawless, but the motherboard manual (and the page I linked to in the OP) claim that ECC is supported. Are you seeing something I'm missing?
Dirge wrote:If you find this sort of stuff interesting, there is an AMD White-Paper regarding the use of ECC memory in embedded applications.
Linky: http://www.amd.com/us/Documents/47644A_ecc_embedded.pdf
mike@quadrupel:~$ cd /var/log
mike@quadrupel:/var/log$ grep EDAC dmesg
[ 9.647486] EDAC MC: Ver: 2.1.0 Oct 11 2011
[ 9.669510] EDAC amd64_edac: Ver: 3.2.0 Oct 11 2011
[ 9.677842] EDAC amd64: ECC is enabled by BIOS.
[ 9.677878] EDAC MC: F10h CPU detected
[ 9.677888] EDAC amd64: f10_probe_valid_hardware() This machine is running with DDR3 memory. This is not currently supported. DCHR0=0x3f58090d DCHR1=0x3f58090d
[ 9.677890] EDAC amd64: Contact 'amd64_edac' module MAINTAINER to help add support.
mike@quadrupel:/var/log$
EDAC MC: Ver: 2.1.0
EDAC MC0: Giving out device to 'i3200_edac' 'i3200': DEV 0000:00:00.0
less dmesg
[ 21.607384] EDAC MC: Ver: 2.1.0
[ 21.610147] XGIfb: Framebuffer at 0xf4000000, mapped to 0xffffc90013800000, size 32768k
[ 21.610150] XGIfb: MMIO at 0xfbcc0000, mapped to 0xffffc90000c80000, size 256k
[ 21.610152] XGIfb: XGIInitNew() ...12345678910111215171818118218318618719202122232425OK
[ 21.619475] XGIfb: No or unknown bridge type detected
[ 21.619478] XGIfb: Default mode is 800x600x16 (60Hz)
[ 21.619499] intel_rng: FWH not detected
[ 21.622244] XGIfb: Added MTRRs
[ 21.622448] fbcon: (fb0) is primary device
[ 21.624433] XGIfb: var->pixclock=25000, htotal=1056, vtotal=1256
[ 21.624436] XGIfb: Change mode to 800x600x16-60Hz
[ 21.634996] Console: switching to colour frame buffer device 100x37
[ 21.644353] fb0: frame buffer device, Version 0.8.01
[ 21.646513] EDAC MC0: Giving out device to 'i3200_edac' 'i3200': DEV 0000:00:00.0
[ 21.689529] leds_ss4200: no LED devices found
[ 21.864868] sky2 0000:03:00.0: eth0: enabling interface
[ 21.865580] ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 21.875503] sky2 0000:02:00.0: eth1: enabling interface
[ 21.876861] ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 21.932076] init: failsafe main process (2920) killed by TERM signal
wibeasley wrote:I hope so, but I'm skeptical. Did you omit that line for the first post this morning?