Damn, wished I had seen this thread a bit earlier. I actually LOVE writing VHDL - resp. designing RTL (Register Transfer Logic) - and consider myself not too shabby at it, sadly my work offers such projects only from time to time. So i hope my input is still somewhat useful and not too late for you/somebody.
just brew it! wrote:As a side note, the VHDL texts I read while coming up the learning curve taught me the language constructs, but did not do a very good job of preparing me for the reality of writing code for synthesis.
THIS. The first problem regarding most VHDL-Courses/books is that it is treated as a programming language, which it is not. It's a hardware description language. A good developer needs not just to know the language, but also the capabilities of the target device (FPGA) or design library (ASIC), and testing/verification of course. Basically you have to know how a certain language construct you use, e.g., a FSM or datapath, will actually get synthesized, and how to verify functionality in simulation and hardware. "Knowing VHDL" then becomes: deriving RTL-synthesisable VHDL-code for a given algorithm.
The second and third problems are 'style' and 'abstraction levels' - hardly any books or courses teach you how to properly style and document code and how to modularize it so it stays manageable and in easier to grasp code-chunks. It's not just 'what' you write, but also 'how' you write it, e.g., a cleanly written, well structured FSM controlling some datapath can already be a work of art; which is apparently hard, for they are quite rare to find in the 'wild'.
Enough of the ranting, here's the best book I found that actually addresses these problems - mostly the first - at least as good as any single book can: RTL Hardware Design Using VHDL - Coding for Efficiency, Portability, and Scalability - Pong P. Chu
It's worth every cent as it actually teaches some methodologies. So far as I can tell most of the other books mentioned so far are mostly along the lines of: ok, here are some VHDL constructs and some/a lot of examples; have fun. To get to know your design-target(s) and tools there is no other way but to dig through your providers documentation, sorry. But if you have done it once, it becomes easier for the next one as there are lots of similarities.
Here's one other link list with lots of good stuff and some more learning texts/FAQs:http://tams-www.informatik.uni-hamburg.de/vhdl/
This is all I can think of right now, feel free to ask more questions.