Why DDR4? Why not straight to DDR5?

[MethylONE]

I haven't found this question answered to my satisfaction anywhere and I thought maybe this would be the place.

We already have solid manufacturing of DDR5 in place and have for some time. Why are Intel and AMD going with DDR4 next, instead of must moving directly to DDR5? I know that DDR5 is expensive relative to DDR3 right now but DDR4 is going to cost more as well and 5 will come down in price once everyone is making it.

Anyone have the answer?

[yogibbear]

GDDR5 =! DDR5

[MethylONE]

GDDR5 =! DDR5

That means 'does not equal' I take it?

[grantmeaname]

Yes, that's what that means.

[Ryhadar]

If I recall correctly the same logic that went into GDDR5 is in DDR3 (or vice versa). Whatever the case may be, DDR3 and GDDR5 are pretty close in terms of performance even though GDDR5 came first (if I recall correctly). The reason being, I think, is because every year you have a new GPU from both camps; they can take advantage of the new tech faster. For CPUs to do that, not only would they need a memory controller upgrade but it means a new motherboard as well, which could result in a loss of sales from OEMs and system builders. So, Intel and AMD only do it when it's convenient.

Also, I think GDDR4 was really nothing more than a speed boost and a die shrink from GDDR3. Rest assured, DDR4 should be faster than GDDR5 -- though it's not likely most consumers will benefit from the added memory bandwidth anyway.

[ImSpartacus]

If I recall correctly the same logic that went into GDDR5 is in DDR3 (or vice versa). Whatever the case may be, DDR3 and GDDR5 are pretty close in terms of performance even though GDDR5 came first (if I recall correctly). The reason being, I think, is because every year you have a new GPU from both camps; they can take advantage of the new tech faster. For CPUs to do that, not only would they need a memory controller upgrade but it means a new motherboard as well, which could result in a loss of sales from OEMs and system builders. So, Intel and AMD only do it when it's convenient.

Also, I think GDDR4 was really nothing more than a speed boost and a die shrink from GDDR3. Rest assured, DDR4 should be faster than GDDR5 -- though it's not likely most consumers will benefit from the added memory bandwidth anyway.

With integrated GPUs being more and more popular, future CPUs (errr SoCs?) might need DDR4 sooner than you might think.

I think Haswell is going to feature embedded DRAM ("L4 cache") to mitigate this problem.

[Scrotos]

GDDR5 =! DDR5

That means 'does not equal' I take it?

I've never seen =! mean "not equal". Programming-wise, it seems to me that ! means "not" and people tend to write out != for "not equal". I read =! as "equal not".

The other popular convention being <>. I can see why Meth would be confused.

[Ryhadar]

If I recall correctly the same logic that went into GDDR5 is in DDR3 (or vice versa). Whatever the case may be, DDR3 and GDDR5 are pretty close in terms of performance even though GDDR5 came first (if I recall correctly). The reason being, I think, is because every year you have a new GPU from both camps; they can take advantage of the new tech faster. For CPUs to do that, not only would they need a memory controller upgrade but it means a new motherboard as well, which could result in a loss of sales from OEMs and system builders. So, Intel and AMD only do it when it's convenient.

Also, I think GDDR4 was really nothing more than a speed boost and a die shrink from GDDR3. Rest assured, DDR4 should be faster than GDDR5 -- though it's not likely most consumers will benefit from the added memory bandwidth anyway.

With integrated GPUs being more and more popular, future CPUs (errr SoCs?) might need DDR4 sooner than you might think.

I think Haswell is going to feature embedded DRAM ("L4 cache") to mitigate this problem.

That's actually a good point. I had forgotten all about iGPUs being able to take advantage of the bandwidth.

[MethylONE]

Well, the '2' in DDR2 stood for 2 operations per cycle, correct? Did that number turn into a generation designation? The reason I had DDR5 being more or less GDDR5 was because I thought the '5' stood for something related to the ops per cycle. If it just means '5th generation' of GDDR then this makes more sense I guess.

EDIT: Just reading what I wrote made something sink in, the 'D' is Double obviously, so the 2 is a generational designation. A small light just went on...

[Scrotos]

Wiki cut and pasting:

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200MB/s.

With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.

[DDR4] is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface, and other factors. [I think they just didn't want to do the math]

...

So DDR did stand for double data rate it first over SDR. PC133 memory turned into PC266 DDR, i.e. 2x of regular RAM. Looks like in DDR2 they added a bus multiplier so it was kinda like a DDDR, 4x. Then DDR3 upped the bus multiplier, DDDDR, 8x. DDR4 does some point-to-point junk that I was too lazy to read but you can probably do some math to figure out the transfer rates and differences.

[Scrotos]

And as others have already pointed out, GDDR numbering is unrelated to anything.

GDDR2 uses the same voltage as DDR, 2.5V.
GDDR3 uses the same voltage as DDR2, 1.8V (or sometimes 2V).
GDDR4 uses the same voltage as DDR3, 1.5V. Only around for about a year and only ATI used it.
GDDR5 uses the same voltage as DDR3, 1.5V.

The same voltages are the generation of DDR that GDDR is based on. There are some specific tweaks made that make GDDR better suited for video card implementations though you'd want some EE here to explain what the prefetch and signalling and junk does as a benefit. GDDR basically did skip "4" and go right to "5" but I'm unsure of the politics or tech involved in why that designation was so short-lived. And why did they start with GDDR2 instead of making it GDDR to match with the DDR tech it was based on? Just a stupid, random numbering scheme.

[axeman]

I'm no EE, but I gather this much: The GDDRx variants make concessions to the specifications that sacrifice things like latency and power consumption in exchange for much higher bandwidth. Therefore, pretty much irrelevant to what plugs into your mainboard.

[superjawes]

I'm no EE, but I gather this much: The GDDRx variants make concessions to the specifications that sacrifice things like latency and power consumption in exchange for much higher bandwidth. Therefore, pretty much irrelevant to what plugs into your mainboard.

I would have to read the specification, but there is probably something to this.

DDR3 comes in 240-pin sticks, but the actual memory is on little pieces of silicon. On lower end modules, you can see these black rectangles on the stick. With GDDR, those same bits of silicon are soldered right into the same board as the GPU and can connect directly. That's not necessarily a concession to regular specification (since the silicon is the same), but you can virtually ignore the interface and can probably make better use of the available bandwidth.

As for naming conventions, keep in mind that the DDR specification (and virtually every professional specification) is not exclusive to consumer parts, so while you may not have seen a GDDRx, that does not mean that it was not used in a more hidden application (heck, some electronics are way behind the leading specifications because they are cheap and reliable). On top of that, getting the letters and numbers of a specification to mean anything can be tricky business, especially when a lot of things are going on and competitors are using difference strategies.

[Scrotos]

JEDEC came up with both DDR and GDDR, I believe, so there's no good reason for the numbers to not be synched. I don't think there are any "hidden" applications for memory specifications, though. I know what you mean but I don't believe it applies in this case.

I do agree with you about the last bit, though. Why else would Firefox decide to increment version numbers like no tomorrow? Because Chrome did it and I guess Mozilla thought the perception was that Firefox was old and outdated.

[just brew it!]

I'm no EE, but I gather this much: The GDDRx variants make concessions to the specifications that sacrifice things like latency and power consumption in exchange for much higher bandwidth. Therefore, pretty much irrelevant to what plugs into your mainboard.

Yup. GDDRx is a completely different animal. The chips are soldered directly to the video card, physically close to the GPU. OTOH "regular" DRAM needs to work when connected to a memory bus through a socket on a motherboard. The DRAM chips on a DIMM are electrically farther away from the CPU's memory controller, and the sockets introduce signal degradation as well.

Electrical signals start to do strange things at really high frequencies. At high enough rates the speed of light becomes a factor as the physical length of the electrical pulses along the wire approaches the length of the wire itself. For PC memories, we're already there! Any discontinuities in the wire (such as a socket, or even the far end of the wire itself) can cause the signal to reflect back on itself, garbling the signal and corrupting the data. Minuscule differences in length or impedance between different traces on a bus can also cause signals that are supposed to arrive together to arrive skewed from each other. Most of the advances in DRAM technology as we've progressed from "classic" SDRAM to DDR, DDR2, DDR3 and beyond have been in the form of increasingly sophisticated ways of dealing with these signal integrity issues; and these issues are much worse for a DRAM chip that is going to live on a DIMM, versus one that will be used on a video card.

Edit: Another way to look at it is, signals on a high speed bus behave like water waves flowing through a bunch of parallel channels. Wherever the channels branch, change depth/width, or end, the waves will be distorted and/or reflected to some extent; and any differences in the physical characteristics of the channels will cause waves in some channels to arrive ahead of others.

[superjawes]

I do agree with you about the last bit, though. Why else would Firefox decide to increment version numbers like no tomorrow? Because Chrome did it and I guess Mozilla thought the perception was that Firefox was old and outdated.

Now I'm curious to see what Apple might do when/if Microsoft moves on to Windows 10...

[moresmarterthanspock]

I'm drinking more coffee, as well as more mountain dew. More work, less time! Whhhaaaaaa!!!! I'm going to need DDR4, and maybe some 15 hour energy drink too!!!!!

[just brew it!]

I'm drinking more coffee, as well as more mountain dew. More work, less time! Whhhaaaaaa!!!! I'm going to need DDR4, and maybe some 15 hour energy drink too!!!!!

Careful with that overclock there... wouldn't want to cause any instability or burn something out!

[ronch]

Er.. because 4 comes after 3? o_O

[Airmantharp]

Wiki cut and pasting:

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200MB/s.

With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.

[DDR4] is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface, and other factors. [I think they just didn't want to do the math]

...

So DDR did stand for double data rate it first over SDR. PC133 memory turned into PC266 DDR, i.e. 2x of regular RAM. Looks like in DDR2 they added a bus multiplier so it was kinda like a DDDR, 4x. Then DDR3 upped the bus multiplier, DDDDR, 8x. DDR4 does some point-to-point junk that I was too lazy to read but you can probably do some math to figure out the transfer rates and differences.

If this is true, it's news to me. I was under the impression that DDR and DDR2 were identical, except that the DDR2 design traded latency for higher clockspeeds, and there was no increase in bits-per-clock. I understood that DDR3 was faster per clock though.

As for (G)DDRx numbering goes, I assume that it's generational, but that there is no correlation between a particular DDRx and GDDRx. Given that the configuration and trace-lengths are different for GPU VRAM and DDRx-DIMMs, I'd expect them to develop independently.

[NeelyCam]

Yup. GDDRx is a completely different animal. The chips are soldered directly to the video card, physically close to the GPU. OTOH "regular" DRAM needs to work when connected to a memory bus through a socket on a motherboard. The DRAM chips on a DIMM are electrically farther away from the CPU's memory controller, and the sockets introduce signal degradation as well.

Electrical signals start to do strange things at really high frequencies. At high enough rates the speed of light becomes a factor as the physical length of the electrical pulses along the wire approaches the length of the wire itself. For PC memories, we're already there! Any discontinuities in the wire (such as a socket, or even the far end of the wire itself) can cause the signal to reflect back on itself, garbling the signal and corrupting the data. Minuscule differences in length or impedance between different traces on a bus can also cause signals that are supposed to arrive together to arrive skewed from each other. Most of the advances in DRAM technology as we've progressed from "classic" SDRAM to DDR, DDR2, DDR3 and beyond have been in the form of increasingly sophisticated ways of dealing with these signal integrity issues; and these issues are much worse for a DRAM chip that is going to live on a DIMM, versus one that will be used on a video card.

Edit: Another way to look at it is, signals on a high speed bus behave like water waves flowing through a bunch of parallel channels. Wherever the channels branch, change depth/width, or end, the waves will be distorted and/or reflected to some extent; and any differences in the physical characteristics of the channels will cause waves in some channels to arrive ahead of others.

I just wanted to say that this was an excellent post; the water wave is such a good way to (try to) explain this! And you know what you're talking about.

[Captain Ned]

Edit: Another way to look at it is, signals on a high speed bus behave like water waves flowing through a bunch of parallel channels. Wherever the channels branch, change depth/width, or end, the waves will be distorted and/or reflected to some extent; and any differences in the physical characteristics of the channels will cause waves in some channels to arrive ahead of others.

Ah, the dual-slit experiment.

[Scrotos]

Edit: Another way to look at it is, signals on a high speed bus behave like water waves flowing through a bunch of parallel channels. Wherever the channels branch, change depth/width, or end, the waves will be distorted and/or reflected to some extent; and any differences in the physical characteristics of the channels will cause waves in some channels to arrive ahead of others.

Ah, the dual-slit experiment.

Reminds me of the last panel of this: http://angryflower.com/schrod.gif

[Scrotos]

Wiki cut and pasting:

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200MB/s.

With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.

[DDR4] is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface, and other factors. [I think they just didn't want to do the math]

...

So DDR did stand for double data rate it first over SDR. PC133 memory turned into PC266 DDR, i.e. 2x of regular RAM. Looks like in DDR2 they added a bus multiplier so it was kinda like a DDDR, 4x. Then DDR3 upped the bus multiplier, DDDDR, 8x. DDR4 does some point-to-point junk that I was too lazy to read but you can probably do some math to figure out the transfer rates and differences.

If this is true, it's news to me. I was under the impression that DDR and DDR2 were identical, except that the DDR2 design traded latency for higher clockspeeds, and there was no increase in bits-per-clock. I understood that DDR3 was faster per clock though.

As for (G)DDRx numbering goes, I assume that it's generational, but that there is no correlation between a particular DDRx and GDDRx. Given that the configuration and trace-lengths are different for GPU VRAM and DDRx-DIMMs, I'd expect them to develop independently.

It doesn't look as though there are any bits increasing per clock, just clock multipliers. I tend to not doubt wiki stuff with technical things because typically really nerdy people have time on their hands and like to show off their technical skill by contributing to articles like this. Same reason why I don't doubt the content of any wiki Star Trek or marvel/dc comic articles. Political or controversal stuff? Yeah, the content is suspect. But techy stuff? Probably true.

The stuff I read on GDDR indicated it was basically a tweaked version of whatever DDR was doing at the time. Why the numbering was jacked up, who knows. Maybe "GDDR" by itself was trademarked somewhere.

[Jason181]

This page shows game scaling with Trinity's IGP using progressively faster RAM.

The problem is that someone buying a cpu and using the integrated graphics even when gaming would probably be better served by getting a cheap discrete card than paying for significantly faster RAM to boost GPU speeds. At first, the additional bandwidth of any new technology will ironically not be used where it's needed most, but as the baseline moves up the situation will improve somewhat.

It seems for ages now that integrated GPUs (whether on the CPU die or on the mobo) have been trying to achieve acceptable performance, but the road has been extremely slow, in part due to the aforementioned conundrum. It is improving, and the rate of improvement is ramping up. It's just that discrete GPUs aren't standing still.

[Firestarter]

I was under the impression that DDR and DDR2 were identical, except that the DDR2 design traded latency for higher clockspeeds, and there was no increase in bits-per-clock.

Well, without going into what makes DDR2 different from DDR (I don't know the specifics either), I can tell you that while bandwidth has been going up, latency has not been shrinking as fast. This has been true for each generation, just compare the CAS latencies between SDR, DDR, DDR2 and DDR3. With current speeds, DDR3 often needs 9 cycles CAS latency. SDR RAM used to have just 2 or 3 cycles, although the clock rate was much lower.

[Dygear]

The other popular convention being <>. I can see why Meth would be confused.

Mainly popular with Visual Basic programmers.

[Waco]

Well, without going into what makes DDR2 different from DDR (I don't know the specifics either), I can tell you that while bandwidth has been going up, latency has not been shrinking as fast. This has been true for each generation, just compare the CAS latencies between SDR, DDR, DDR2 and DDR3. With current speeds, DDR3 often needs 9 cycles CAS latency. SDR RAM used to have just 2 or 3 cycles, although the clock rate was much lower.

2 cycles at 400 MHz is a bit longer than 9 cycles at 2000 MHz...so yeah, the improvement has been marginal at best.

[just brew it!]

The individual RAM cells haven't gotten all that much faster either. The way they've managed to keep increasing the bandwidth is by doing the rough equivalent of RAID-0 inside the DRAM chip, where multiple sets of DRAM cells on the die feed a single external interface. That's also part of the reason the latency has stayed roughly constant in absolute terms -- you still need to wait about the same amount of time for the first set of memory cells to respond before you can start streaming.

Edit: And if you think about it, dual, triple, and quad channel support on motherboards is essentially RAID-0 with DIMMs. Most of the DRAM bandwidth increase over the past 15 years have come from reading/writing more bits at once, not from making the individual DRAM cells faster.