![]()
![]()
| Edit Reply |
|
Proesterchen |
That just about seals an 18(+)-months dominance of Core 2 Duo / Extreme / Quadro in the market. Intel can make this a bloodbath, but that's what AMD deserves for sitting on their lazy behinds, IMHO.
. btw: Given AMD's track record with the introduction of new microarchitectures, that plus up there might extend quite a bit. |
![]()
![]()
| Edit Reply |
|
axeman |
I believe him, AMD's biggest problem is being short on resources, so their R&D process takes a while. But they certainly seem to put more forthought into their designs, which is good because they pretty much are stuck putting all their eggs in one basket. The last two major architectures turned the PC world on its ear when they _finally_ released them (the Athlon 64 and the original Athlon). I expect nothing less from the K10 (I believe what was supposed to be the K9 was dropped, probably 'cause it was a dog).
|
![]()
| Edit Reply |
|
IntelMole |
Wow. Talk about short on details. It is time to roll out the trusty sarcastic competition response once again:
I, IntelMole, am also planning a new microarchitecture for 2008. It's going to be so good, it'll have naughty nights in with Core's mum. -Mole |
![]()
| Edit Reply |
|
UberGerbil |
K8L has been pretty-obviously a stop-gap from day one. Even the name suggests that (though AMD's own people claim they're not sure where that name came from). AMD is just going to have to struggle through this summer's Intel hypefest (and price bloodbath) until they have something new they can actually show. The real question is how realistic that late-2007/early-2008 timeframe for the new design is, and also whether thay can keep their process-shrink and fab-enlargement plans on track so that they can produce a new design in quantity at a healthy profit.
|
![]()
![]()
|
Jazztags: (they MUST be closed) r{ red }r g{ green }g /[ italic ]/ *[ bold ]* _[ underline ]_ -[ |
http://www.mikeshardware.co.uk/Roadmap20XX.htm
AMD Athlon 64 (Greyhound) is expected to be released in H1 2008 on a 65nm process. Greyhound is expected to be the first K8L based CPU, featuring 4 cores. Each core will feature 64KB - 32KB Instruction, 32KB Data - of L1 (down from 128KB in the K8 architecture), 512KB of L2 cache per core and - in it's Opteron form, 2MB of shared L3 cache. K8L will also feature AMD's DICE (Dynamic Independent Core Engagement) power saving technology which enables each core to alter it's own p-state (Power state) right down to putting a core in a full Halt condition and will introduce HyperTransport 3. Hypertransport 3 will introduce a number of improvements. Firstly, the HT speed will be increased to 2.6Ghz, which will allow for 5.2GT/s, compared with a maximum of 1.4Ghz in HT2 (1Ghz in the K8 architecture). Secondly HT3 will introduce 'Un Ganging', which will allow either one 16-bit link or two 8-bit links to be created on the fly. This will be particularly useful with multi-socket Opteron servers as it can allow for single memory hop access to memory which would previously have taken two hops. Additionally the K8L core will have an enhanced instruction set, Indirect branch prediction, 32-byte prefetch (compared with 16 in the K8 architecture), 48-bit addressing with 1GB pages, better cache coherency, I/O virtualisation, Memory mirroring, data poisoning and HT retry protocol support, and 2x128-bit SSE units (compared with 2x64-bit units in K8) featuring support for single cycle 128-bit instructions. Greyhound will interface to DDR2 memory, with the K8L core featuring support for FBD and, in a future memory controller revision, DDR3 and FBD2 support.
Rev G is meant to be the stopgap, at the end of 2006.