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| #10. Posted at 02:40 PM on Oct 25th 2006 | Edit Reply |
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Helmore |
I was wondering where the RAM memory is, I can't seem to find it in the pics, can someone please point it out to me?
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Shining Arcanine |
I think I have an explanation for the greater than 16x performance. The single core processor being used in the comparsion is probably not a Tigerton processor with three cores disabled in the BIOS, but rather the single core version that Intel will be shipping as a budget processor. The performance discrepancy comes from the single core version having less L2 cache avaliable for its core than each of the cores in the Tigerton processor have avaliable. It is the only possible way to describe it.
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karrock |
Damn that's nuts! Who would have thought that there would come a day where we need a huge CPU cooler bolted onto the motherboard's chipset? Sure, we've seen little low-profile sinks, some with fans, and even some small heat pipes, but nothing that looks like it should be attached to an Athlon processor...
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Nuclear |
Notice the four CPU coolers grouped together across the length of the case. Such a layout would likely be impossible without Caneland's point-to-point connection between the chipset and the CPU.
current IBM X365,X366, X460 and newer revision are already doint it, so it's not impossible with the current Xeon implementation |
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Proesterchen |
showing a working 4S, quad-core server >> showing a quad-core MPU wafer of unknown quality
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_Shorty |
"I'm unsure about the reasons for a performance boost of more than 16X"
SIMD? At any rate, it's one run, and there could be any number of reasons for a large margin of error. edit - not to mention some of their cache memory is shared, so there would be some help there, too. A single core would have to go to main memory X amount of the time. But with multiple cores sharing some cache, with the help of prefetching, there would likely be some gain from already having data they were going to get already being in cache. |
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lyc |
i think one could see a slightly super-linear speedup due to there being fewer accesses to main memory, with increasingly large parts of the dataset residing in l2.
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Shintai |
Omg, its an nvidia chipset cooler!...oh way :P
Anyway, cute box...on friday I might get a cloverton box... |
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morphine |
Give how sweet this looks for servers and heavy workstations, I propose it's renamed "Candyland".
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