The correct acronym for Hyper Threading is HTT, not HT. Good thing this article does not discuss HT too or things could get confusing. ;)

Interesting if true. HT is a fundamentally sound idea for keeping a given number of execution units loaded, if they design for it from the ground up I'm sure they'll do it right.

I guess the question is, is there a point to even using hyperthreading? You already have 4 cores. You would have to make your whole architecture wider to even see benefits, and then only with specialized software. Would you be better off just adding more cores instead?

What is the transistor cost for widening your architecture vs adding more cores? Widening the architecture wouldn't take that many transistors or would it?

#1 You are joking right?

Thanks to its short pipeline an good branch predicter C2D will probably not benefit from hyperthreading all that much

While the shorter pipeline makes the Core 2 architecture less of a candidate for SMT, the wider execution resources argue the other way. But if you're already got two cores, SMT isn't going to buy you a lot of returns for desktop apps (including games) even in cases where it does fully exploit otherwise dormant execution resources... and it uses more power, likely making the performance/watt equation worse.

On the server side, however, the equation is different because many server loads scale very well with processors, real or virtual. Note that all the recent high-end server chips (Montecito and POWER5/5+, not to mention Sun's Niagara) implement SMT (some fine, some coarse). I wouldn't be surprised to see Hyperthreading return in future server chips (and have predicted as much when this debate arose in the past), but it's not all that interesting for desktop/mobile chips (though if it's available Intel will undoubtedly make the tech a feature of future "extreme" desktop chips).

#19 By 2009, I would hope that would describe the Celeron processor. Kinda hard to imagine a dual core celeron with hyperthreading though. If that was the case 99% of people would never even buy midrange chips.

maybe by that time we may actually have software that requires a quad core cpu (will need to be better than dual core with typerthreading). Who knows... (notice i said requires, not benefits from)

#6. If that's true we should see quite a benefit from software with the required amout of threads right? How much of an improvement do you think we'll see on average? Also, do you think it will decrease performance if HT is on and only 4 threads instead of 8 are used? (assuming the processor is quad core) The P4 had a nasty habit of doing that

HT is a fad that sould be called SMT.

Real SMP pwns SMT. ;)

Hmm, I can see reasons for both Shintai's and Choas' points being correct. C2D is already quite efficient at what it does, but HT might be able to boost efficiency if done right.

I think the point we probably should take from this though is that it will be implemented in a 2008 product, and as such we might not know what other internal tricks that Intel would put in that could make HT much more effective than it was in the P4's, or how the base C2D architecture might change.

Can someone explain why there would need to be 1,366 pins? I understand it's got the memory controller built in now but that should only take 480 pins right? What are the rest for?

C2D is also better suited for HT than P4, more resources are wasted in the C2D.