Somewhat OT, but my Opteron 165's corresponding latencies (via CPUz 1.38) are:
512/512: 13nS (versus 5ns on 90nM 5000+)
8192/512: 109nS (versus 50nS on 90nM 5000+)

This is with the Opteron (also a 90nM part) running at 2.8GHz, while the 5000+ runs at 2.6GHz. I realize the Opteron's L2 cache is twice the size, but this wouldn't explain why the L1 cache access times are so much slower. Am I missing something here?

Ad has a fair number of weak spots cache is one of them.

Anandtech received a reply from AMD as to why the cache latency is higher. Supposedly it is to give AMD an option to use much larger L2 caches in the future.

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2893&p=3

AMD has given us the official confirmation that L2 cache latencies have increased, and that it purposefully did so in order to allow for the possibility of moving to larger cache sizes in future parts. AMD stressed that this wasn't a pre-announcement of larger cache parts to come, but rather a preparation should the need be there to move to a vastly larger L2...

Here is a little reality check for the raving fanboys.

Who acutally cares about this stuff? Performance freaks and die-hard fanboys. How much do they make-up the market? like >2%.

What are 65nm A64 being marketed towards? OEM a.k.a (average joe and jane rigs). Do they care about sightly higher latency? Not in the a single damm.

I do think it is a lot more interesting to figure out what is exactly causing the difference from a technical standpoint.

Nice follow up TR.

AMD's playing it pretty shady lately with their launches. I guess if they had a horn to toot they'd be tooting it, but this wouldn't look like such a conspiracy if they'd just go ahead and give full disclosure. What could have been a mole hill will now be a mountain; it's going to be a feeding frenzy.

Eh,

FWIW, maybe you could do some sort of negative overlay of those two graphs, cause I can't tell a damn bit of difference just looking at them.

Well, so long AMD and thanks for all the fish'n'chips!

I'm actually finishing up an article that will probably shed a lot of light on this issue. There are actually many, many factors that are not considered by either TR and Anand (this article has actually been a work in progress for the past week for me, and the results that both TR and AT have spotlighted have filled in some gaps for me). Hopefully my analysis of the situation will be accurate, and that Shin and Proest will be kind in their criticisms ;P

...and if I may put my speculation hat on for a moment:

Perhaps the L2 cache was the stumbling block when it came to clock speed scaling. If so, then intentionally adding some latency to the L2 cache may permit the 65nm core to scale to higher clock speeds, at the price of a slight decrease in IPC.

Thanks for the update, Scott!

I'm definetly looking forward to see what AMD has to say about this, and where exactly this lowers performance and by how much.

Thanks for the 3d cache latency graphs Scott.

These results, here and elsewhere like anandtech, beg the question of why this chip was released in the first place. Ya gotta wonder if there wasn't some failure in QA + PR + administrative oversight vs. manufacturing per se. As others have suggested, a first run of 65nm might not yield the best performance. That's fine, but then why release them days before Christmas? AMD as scrooge? BTW, in the interests of full disclosure, all my systems are AMD, and I still have a lot of faith in the company.

Heh, just thought of a funny up-side to all this: now 939 chips look even better. Eh, so do C2Ds.

Is that my foot or a rifle target?

Whoa... funky.

I wonder if this will be fixed in the next stepping?

do you think you could put that post in as an addendum for the original article? ie - page 6?

yknow, like some kind of Christmas present for Proesterchen. ;)

I bet this has to do with getting yields up and possibly die sizes down.
In less then six months this product is going to be low end stuff for the likes of dell and HP. Altair isn't that far around the corner.