AMD, Intel, and others have stated that at 65nm and i believe even back at 90nm they are mostly just shrinking gates lengths, not feature (transistor) sizes.

Heh I was warned over a year ago not to buy any amd chip based puter unless they went to AT LEAST 2 meg cache.

The reason is obvious enough if your in the game making industry.

Currently amd depends on smallest die size possible and gets it with small caches. But they cant do that much longer. And well they arnt known for thier cache designs.

i don't see this as a surprise
from memory amd had used combinations of old and new process tech's
e.g 180/130nm hybrid, 130/90nm hybrid
they keep doing so til it's fully transitioned
and they call this process "tweaking"

90nm was a pain (again from memory) intel, ibm, and amd all had issues when scaling clockspeeds on their initial 90nm. power increased exponentially approaching 3ghz so you didn't see powerpc/amd chips clocked that high in retail. intel however didn't seem to care and went ahead anyway.

also no offence but a bit worrying having a physicist that can't spell the profession....

Are we talking about additional L2 cache?

Or could this have something to do with thier plans to add L3 cache later on?

Hmmm, maybe for very large Z-RAM cache? Does'nt Z-RAM have slightly higher latency anyway?

http://www.lostcircuits.com/memory/zram/

http://techreport.com/onearticle.x/11371

Just want to make a point:

A lot is being made of some performance hits that leave, say, a 65nm 4800 slower than a 90nm 4600 in some places. I think we will all agree that if the former is still faster than the latter in aggregate that the chip numbering still makes sense. This does mean that, if you go with and AMD chip (and if you are obsessive about low res frame counts, Linpack, Super-Pi, etc), you will have to pay closer attention than ever to which particular model of chip excels at your specific usage pattern. The other option is to just get a C2D, or grab a 939 Opteron while they last.

None the less, until AMD breaks away from its current performance rating system, such criticisms as have been made here are still fair game.

Speculation: As for troubles AMD has with getting to new processes, I continue to think that this has more to do with the fact that they don't have spare fab space that they can take off-line and just hand over to process engineers.

I still wonder how AMDs PR spinning is working against the massive gaming performance drop.

http://www.firingsquad.com/hardware/amd_athlon_64_4800_65-nm_previe...

Two years ago AMD's Jerry Moench talked about a future CPUs L2 cache, which would actually run at a lower clock speed than the core. At that time this has been referred to as being K9 stuff.

Now it is for bigger L2. And for a DC they might replace L3 with more L2 instead, which is faster, but not shared and has the same SRAM density. The L3 logic and tags on a K8L dual core could also be left out.

This latency might even allow AMD to implement shared L2s between 2 cores. And it seems, they implemented it into the 65nm core (where Brisbane already has most of the changes, which we find in Barcelona's cores) for the future. This means, they want to use the K8L core for some time in their building block system. Changed L2 latency means a lot of changes to the core. So this core would be prepared for any L2, which needs up to these 20 cycles.

The 126 mm² cores have been shown in june or july on some analyst day. There was a 65nm wafer with long (or wide, as you prefer) dies of that size.

"AMD's model of continuous, gradual improvement to its manufacturing techniques. "
Increased latency isn't an 'improvement' for the consumers though is it now?
But they never said their 'improvements' would benefit those of course.

Yikes the heavy hitters are here today.....interesting stuff guys,good to see you on board Jack.

So...same clock speed, same cache size, same bus speeds and memory speeds, and higher cache latency, but still the same performance rating/model number? Kinda...sneaky. Well I guess technically it's a different model name with the EE on it, but still, it's not ACTUALLY 5000+ if the other one is 5000+, but they can claim that the EE must be considered with the 5000+ and is an indicator that it's a model with slightly different performance than the other one even though it's got the same Performance Rating.

With the K8L half a year away, why would AMD make this change to the K8 which is nearing EOL? I can see a possible need for larger caches in the K8L's future but not the K8.

One or two other explanations for the non-linear reduction in die size.

1) "65nm" and "90nm" doesn't mean that every transistor has that feature size. For whatever reason (interference from other nearby lines, maybe, or just a need to ramp signal power quicker and thus use a bigger transistor), various parts of the chip will have larger or smaller feature sizes.

2) Moving to smaller process geometries gets tougher the smaller you go. Things like path length, interference, power density, and the speed of light are all factors in the design. As such, the design is normally tweaked a little. Witness Thoroughbed A, which was a 130nm shrink of a 180nm chip. It developed a problem with one or two layers of the design forming a capacitive link as I recall, and needed adjustment to become Thoroughbred B, which scaled as expected. Anyways, point is, it's not as simple as "make transistors smaller, hur faster smaller chip hur." It's more like "make the transistors smaller, then tweak the design till they work, then test it to make sure it's identical, then it's a smaller faster chip." 1) is probably implied by this point also.

Damage's reply could be very punny. Physically larger, you say?

I read this as AMD had the L2 cache very tightly spaced on the 90nm cores, and also very densely laid out. When the shift to the 65nm node came, they laid the L2 out rather sparsely. This gets L2 yields way up in the short term, and has die space pre-provisioned for higher capacity dense L2s once the 65nm process is more familiar. That will probably also bring a small performance boost, as well.

It's not that they have 1/2MB L2s with half disabled, they have .5/1MB L2s spread out over a 1/2MB area.

No rebuttle from shin yet? he must be slacking :rolleyes: