If you look at the Athalon website, you will see that they are going to ship the .13 micron T-Berd later this quarter with the 256k L2 cache, but later on they are going to make an AMD Athalon code named the Barton or something, with the 512k of L2 cache, this is in their processor roadmap, a handy place indeed!

Looks like you are vindicated Forge for all those who doubted. Barton has 512 KB of L2 cache (Indicated by AMD)

Originally Posted by GiGNiC
got a nice 512KB L2 Athlon aswell, but I can\'t seem to fit it in the socket ;(

Yeah Yeah, Slot A Athlons not included :)

I actually had the same thing myself until exactly a week ago, then i upgraded it to a Slot A Tbird, so ive only got 256K now...

LOL.. MY Athlon DOES have 512Kb L2 Cache.. And I can prove it. So if you want a 512Kb L2 cached Athlon, just gimme a call ! ;D

Originally Posted by GiGNiC
that was: german tech sites / the inq / the reg
not: german tech sites: the inq / the reg

noticable difference

[quote]herd about it first from one of thous German tech sites, The Register or The Inquirer ?????
[/quote]
I'm sure they'll be the most surprised to learn they're German....
Bloody 'ell

Originally Posted by GiGNiC
or there will not be a 150Mhz bus at all
if the FSB goes up, it will be either 166Mhz, or all the way to 200Mhz, this keeps it at easy sync with RAM-speeds that are/will be available

my € 0.02

There absolutely will not be an official 150 FSB from AMD any time soon.

Eating blank lines at the begginning of messages would be great too. ;-)

It is incredible how much attention and irrelevant controversy a typo can generate

Another thing to consider about is……Don’t you think that if the upcoming T was going to have a 512k L2 cache we would have herd about it first from one of thous German tech sites, The Register or The Inquirer ?????

I wish they would add something to eat blank lines at the end of messages, I keep forgetting to clean mine up. :-)

,........,........,........,........, PCI @ 33
,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,., FSB @ 150
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, MEM @ 300 (DDR)

this counter example has the FSB missing every other PCI clock by a hair.

133 / 33 = 4
150 / 33 = 4.5

AG #41

nuclear is right, and I think you are missign the practicallity of it.

I'm sure its true that if they wanted to they could. But usually its some multiple of the PCI bus, and AGP/DMA/South Bridge are usually tied to this as well. Its way easier to do every x number of PCI clocks than to have some bizarre out of sync clock that doesnt match a PCI clock at all.

Tricks like this can be great for overclocking the processor, where the processor can do work without the memory bus, so who cares if it has an extra cycle that it cant transfer on. Usually though you have to drag the FSB and the proc and mem together for doing wierd clocks. Not too long ago you had to drag the PCI up as well.

But making the actual "standard" async with PCI is just goofy.

,.......,.......,.......,......., PCI @ 33
,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,., FSB @ 133
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, MEM @ 266 (DDR)

See how they line up all purty like?

Nuclear, my point was that AMD could go to a frontside bus that ended with xx0 or x50...

Forge.....mobile Duron could be an area for mixup...but I agree hes still a dambass :)

And hes in QA ? buhahaha :)

Originally Posted by nuclear
ag 31
the bus on the athlon 550 trought 1g were 100mhz ddr
the multiplier on the cpu has nothing to do with the speed increment of the bus speed.
it doesn\'t really matter the final speed of the cpu compared to the increments of the bus.

Originally Posted by GiGNiC
#33 and #35, indeed, they add redundant blocks of cache for \"safety\", but the numbers given by #33 are way to high, that would indeed, as #34 says, be counterproductive, as it would be really \"to much\" redundancy

BTW, credit for that quote goes to the [H] as well.

[q]Just wanted to say thanks for pointing out something we missed. The laptop is not a Thoroughbred proc. It is a mobile Athlon 4 with 64KB on the L2. It has been fixed. Thanks again.

Adam Gernhart
Compaq.com Quality Assurance, Site Operations, and CEMS Administrato/q]

I no longer have any respect for Compaq at all. Those morons guessed again, and guessed wrong AGAIN. The Athlon 4 is only shipping in a 256K L2 version, and he didn't mean L1, cause that's 128K on EVERY K7 core ever.

Dumbasses.

Nor really, AG#34. If the cache presents the highest yield liabiity, throwing out die due to defective cache would waste more silicon than increasing diesize to achieve higher yield.

cunningstunt, I find that doubtful, it would be a HUGE waste of silicon realestate...

I could see them having an extra 32KB of L2 on the die for such purposes, but not double...

Aside from which, doubling the L2 like that would increase the die size and LOWER the yield.. which would be somewhat counterproductive :)

Originally Posted by CunningStunt
You know that T\'bird & XP Athlons are made with 512k of L2 cache & that the Durons are made with 128k of L2 cache.

It alll comes down to fab yields.

You see the problems comes down to what we could even call cache misses in the fab.

This is why all Intel .18m PIIIs were built with 512k of L2 cache. Those with some iffy cache traces were sold as desktop PIIIs with 256k of L2 cache (as opposed to mobile &Xxeon PIIs which had 512k of L2 cache), those with even more iffy cache traces were sold as Celerons with only 128k of L2 cache.

With the .25m K6-III AMD did not take into account the problem of cache trace misses in the fabs. Consequently AMD had very low yields of K6-III CPUs, which were designed to have 256k L2 caches, & were made with just 256k L2 caches. So any with poor cache traces had to be sold as normal K6-2 CPUs which had no on-core L2 caches. Pull the aluminium heatspreaders off enough K6-2s & you\'ll come across the occasional one with a bigger core (so I\'ve been told).

Consently when it came to their .18m lines AMD decided to take the cache trace problem into account from the start. All K6-3+ were manufactured with 512k of L2 cache, which gave them leeway as the K6-III+ was designed & sold as a 256k L2 cache CPU. If there were any iffy cache traces it was no longer a problem, as half the L2 cache was going to be disabled anyway. Any with more than a few poor cache traces were sold as K6-2+ CPUs which only required 128k of working L2 cache.

& so it was with the .18m Duron & T\'bird lines, both of which were manufactured with double the required L2 cache. The 256k L2 cache T\'bird Athlons were made with 512k of L2 cache & the 64k L2 cache Durons were made with 128k of L2 cache. At the time there was much speculation of why AMD did not release a 512k L2 \"Athlon+\" or a 128k L2 \"Duron+\", to try to make a few extra dollars on their cores with that came out of fab testing with no iffy cache traces.

Search www.theregister.co.uk on \'amd\', \'K6-III\', \'yields\' or \'.18m\', & you\'ll see the many articles they put out on the subject (for some reason one can\'t do multiple word searches on their site - they probably get more page clicks if one can only do single word searches).

AMD have now said it was a typo, but didnt say it doesnt have 512K cache....so just to be difficult ill throw in another option, hehe........my guess is a beffed up 384KB L2 in addition to the normal 128KB L1 = their quoted 512KB ' L2 ' ?

Either that or theeres a new L3 cache (on die / onboard... ? ) and theyre all being pissy ? :P

Herman, uh.. clock increments go up like that because they are using multipliers off a 133Mhz bus

have you forgotten the 950/850/750 Mhz Athlon's already?

Originally Posted by GiGNiC
My current state of mind would be: [i]Confusio/i], which after that will most likely be followed by [i]Not Caring At Al/i] (the right word didn\'t want to pop-up here)

basicly, I\'m leaving the 512KB open as an option, but I\'m not finding it likely :)

This might be something: The message from AMD on [H] denies that the laptop has a T-Bred, but it doesn't deny that the laptop has a 512KB L2. Could just be a P3-M, but maybe....

Must be a slow news day...

Uh, Forge, how much of your soul can I rent for 3 bucks (american)?

SPILL THE BEANS DAMMIT!!!

:)

ER

[q]UPDATE: AMD informs us it was all just a typo:

Definately a typo on the Compaq website... TYPO on the L2 cache.
So there you have it. [/q]

Dang, I gto all happy for nothing.