Also Coppermine has 8-way set associative cache and CII has 4-way set associative cache
Does this make any difference ??
... and http://www.anandtech.com/showdoc.html?i=1227&p=3
"Update (4/21/00): It turns out that WCPUID is in fact misreporting cache
latency. According to Intel, the Coppermine128 Celeron and Coppermine
Pentium III's both have the same cache latency. So much for the latency part
of the theory. But there's more to cache than just latency and clock speed..."

Kirsa

This may clear up some of it:
http://www.anandtech.com/showdoc.html?i=1227

Anyone who has 3DStudio Max Release 1 and a C2 ? The first release is not optimized for MMX nor SSE and can render in L1 cache only. That would be a good way to compare the two CPUs, since L2 configuration does not come into play here.

My few cents, JS

Think of the cache on the C!! as running 2 times per 4 cycles.

Latency 2 means to wait two cycles out of every four. The other two cycles are when it fetches or writes a register to the cache. This means that
each cache is never used more than once per 4 cycles. The staggered timing insures that there is always a cache ready for the core; if the
correct register is in the cache there is never more than a 4 cycle latency in its retreival.

Since the C!! is designed off the P!!! then you have to consider the P!!! architecture. The cache of the P!!! is running 4 times per 4 cycles. This
could be the reason that the P!!! uses four resistors to set up the cache. The P!!! caches may be numbered 0-3; each cycle the cache takes turns
as to which cache is active. Since the C!! caches may be numbered 0-1. After the 2 caches of the C!! run their loop, there is the "2" cycle pause
to make up for the lack of the extra two caches as found in the P!!!.

Each sub-cache may need the 3 cycles off after each use in order to organize itself. If the C!! is programmed to use the same 4-cache loop of the
P!!! then it makes sense that it cannot be altered!

Doesn't this make sense to people? I believe this to be pretty close to the truth. Why else would C!! use 2 resistors to enable only half the
256k of cache; the P!!! uses 4 resistors to enable all of the 256k cache.

Just think, though, if it is true then enabling the other two caches will not catch the C!! up to the P!!!.

It wouldn't unless the number of "dead" caches (during a count through 0-3 it detected two as not active) was the deciding factor if the latency
was 0,1,2, or 3. (I would have to think that enabling one more cache would make the latency "1" if this was true. Likewise, disabling one cache
would raise it to "3".)

It would be easier for someone to disable an extra cache module then to enable one. Anybody with a C!! have the guts to expiriment!?!

Originally Posted by office boy
Yep it did

Office boy:

Did it have an impact on performance on ur old chip ?

Originally Posted by office boy
Don\'t know if any of you are interested in this ;)
but I have a C2 566, and it\'s running in a Bx6R2. The BIOS latency adjustment does not \"stick\" according to WCPUID, and using WCPUL2 has no effect, as it reports not being able to adjust the L2. Since it worked on my old celery 333@515 I’m going to guess that the chip has been latency locked, or at very least the latency is being reported in a different manner and the Bios and H-oda\'s progs can\'t read (or set) it correctly

None of the BIOS on any board tested see a Celeron II. I'm sure that there would be a difference in the way the BIOS would handle 256K ATC cache vs 128K cache vs Celron 128K cache. We need real BIOS support on the motherboard itself to see true performance from the new Celeron IIs. I still beieve that a 533A Celeron FC-370 running at 100 x 8 = 800Mhz would be within 5% of a PIII 800E.

jerry

For the L2 latency, WCPUID is merely displaying bits 1 through 4 of MSR 11Eh in decimal format. The different L2 latency settings on the Coppermine PIII and Celermine (0 vs 2) merely mean that the L2 latency is configured differently. It does tell us how it is different, as the numbers 0 or 2 are unlikely to correspond to actual latency cycles.

Originally Posted by jsteimle
I read somewhere in the last few days (sorry don\'t remember the site, I hit 15-20 HW sites a day) that the Celermine had 2 clock cycles inserted per cache fetch while PIII\'s had none.
Jeff

Howe about this: Intel states that the cache on the CuMins is Advanced Transfer Cache; the same statement is not made for the CelerMine. Most people have dismissed this as a matter of semantics. What if it isn't? What if Intel really has disable the advanced caching featurs of the CuMine? It could make the difference.

Originally Posted by nando
Even if it\'s slower, the Celeron is still cheaper. I still want a P3, as this 566 is kinda crappy (975 with sub freezing water cooling, blah). Maybe a 750 or something. At least then my bus speed would be higher at the same CPU speed (950+), so it would end up being faster anyway.

Ok. Intel in the past (at least from some reports i have heard) has been known to take procs that do not pass full manufacturing specs and resell them as a stepped down version. from what i remember of this claim, the 486SX was a 486DX that the FPU didn't pass inspection. nothing serious to stop operation of the rest of the chip, all you have to do is disable the FPU and remark it. The onboard FPU was a new technology for intel 486. L2 cache was a new technology on the Coppermines. the Celeron II, from what i have seen, looks just like a Coppermine with a different name printed on it and missing a couple of pieces on the bottom. Maybe those adjust the speed of the L2 as well as size. who knows.

Now as far as the speed difference, did they disable anything else? gotta get some serious CPU info tools running on both and compare the results.

Get WCPUL2, it can manualy change the L2 cache latency.

Actually, the Itanium has been in the market for years. Intel just disabled features and sold them as Celeron's /Pii/Piii's

All these programs that proportedly report latency are giving bogus numbers. Fact of the matter is that the latency for the Coppermine's --> L1 <-- is 3. So how can the L2 be 0? Impossible. Intel's spec sheets say the Coppermine's L2 is 7. BTW, the news on JC's says using cachemem to actually benchmark the performance, the C2 and Coppermine L2 has the same latency.

Maybe by halving the cache size they also halved the cachebus width, which is then 128 bit instead of 256. Could explain the loss in performance.....

TazUk:

I can deny it. :)

I'm suprised that this discussion is focusing so much on cache issues. We already know the thing has less cache RAM, but it seems slow in places where cache shouldn't matter so much.

Could be something simple, like programs not recognizing the SSE capabilities of the CII.....

Somebody help me!

I'm stuck in Richard Gere's ass!

Latency on the Coppermine L2 is NOT 0. That is impossible and is simply a bug in whatever program you are using.

Originally Posted by TazUk
From what I\'ve read elsewhere the Celeron II\'s are based on the original, i.e. Katmai, PIII core. Can anyone confirm/deny this?

It think there is a 1st level latency installed in the new celerons.
I tested different 2nd level cahce latency settings with my old celeron@450 and there
was a minimal performance hit

Sweetie

Originally Posted by rock
I think it is time to put this theory that the celeron IIs are reject coppermines to bed. All the Celeron IIs seem to be reporting out as Stepping 3 whereas the coppermines report as Stepping 1.

Escher,

Your hypothesis on the cache is not very plausible. If the chip failed during wafer/module testing of the CuMine,
then Intel might be then running another set of tests to see if it might be a viable CelerMine. Only if either of the
128Kb cache passed, would Intel release those chips. Releasing a chip with bad cache means that there
would be data errors all over the place. The only way to know if its the cache latency is if someone would test
the CelerMine and CuMine with cache disabled at the same freq/bus speed. There's really no way of knowing
how cache intensive any of these apps are, including Quake. There are a bunch of sites out there that have
unlocked engineering samples of CuMines aren't there? We should get one of those people to run these tests.

Originally Posted by rock
I\'ve seen posts from two folks to the affect that you can change the L2 latency in the bios but that it doesn\'t stick. Apparently this has been hardwired somehow. But to all the naysayers/spitfire promoters...take a look at the celeron at 1gig piece over at HardOCP. The numbers are MUCH better than those posted by GamePC. I suspect that GamePC may have gotten a bad engineering sample.

CyruzTheGreat

20. Posted by Anonymous Gerbil
at 02:03 pm
on Apr 13th 2000

My abit BH6 1.0x lets me specify it in CPU SOFTMENU II ..
dunno if it actually werks....

does anyone know if there is a way to change the latency of the cache on teh celeron II?

Badger

Originally Posted by samurai
Ok, so can someone is JAPAN figure out how to open up the chip and turn on the other 128k of L2 with a simple spot weld and a paper clip?

It really does make sense that INTEL would do SOMETHING to cripple the C2. It\'s obvious that whatever tehy did to create the performance gap is working. Seems like many people are sticking to the P3\'s for overclocking... but it\'s pretty early yet. A C2@1000+ would be nice if the price is right. My 300A is getting pretty stale.

Originally Posted by snaz_89
I agree with t44_. If I had access to the hardware I\'d try the following tests.

A PIII Cu and the C2 both with L2 cache disabled and at the same FSB speed. Either underclock the P-III or Overclock the C2.

That way they are on equal battleground. If they perform the same then, we know it is something else. It has already been determined that FSB will make a difference, by having 2 Cu ran a the same MHz speed but at 100 and 133 FSB. So if it is a L2 cache issue we will be aware of that by the mentioned test. The other possibility is that there may be a latency on L1 as well, or something, so you could disable L1 and run the tests.

I was waiting for the .18 Celerons to come out. Not only did they choose not to make them 100 MHz, as their mobile ones are, they seem to have done something else to them. The price differnce between a 600 MHz C2 and a 550 Mhz P3e is probably worth getting the P3, as the perfomeance on the 550 will be so much better. Heck maybe buying a 600 MHz P3e will be the way to go. Major disapointment, by the reviews so far. Who cares if you can overclock it to 1 GHz if it runs like a P3 700.

CyruzTheGreat.

12. Posted by Escher
Of some variation, i agree.. there's a reason for the latency of 2 (which in fact would be 3 right? with the CuMine P3 having one of 0(1))

Still, it would be nice with some beches of a P3 and a Celeron both at 100mhz FSB at same clock, with lev2 disabled..