Via preps bus for speed
Preparing for the advent of DDR SDRAM memory interfaces this fall, Via has announced it's preparing a new means of connecting the North and South bridges on its chipsets. The present interconnect, a standard PCI bus, just won't cut it once new RAM technologies hit the streets. As Via put it:
The 32-bit, 33MHz PCI bus with a peak bandwidth of 133MB/S, is no longer sufficient as the primary bus between the North Bridge and South Bridge and system expansion for advanced PC systems, which are already being equipped with 1GHz processors. Any high-performance system with leading DRAM technology such as DDR SDRAM would be handicapped when paired with a 32-bit/33MHz PCI South Bridge. The system would not be able to fully benefit from advanced DDR SDRAM because the PCI bus has now become the system bottleneck."
Via's alternative, the High-Bandwidth Differential Interconnect Technology (HDIT) architecture, will be able to deliver up to 4.2 GB/second of bandwidth, although initial desktop PC versions should be a quarter that speed or lower, from what I gather. The HDIT architecture should allow some latitude for motherboard makers to build faster solutions for higher-end systems. Via is readying both North and South bridge chipsets capable of using this tech.
Via's announcement is notable because it doesn't mention AMD's efforts to use the Lightning Data Transport (LDT) bus, which I'd suspected Via might use, as well. Intel, of course, already has its "accelerated hub" setup. So HDIT looks like Via's own way. No doubt they'll make North bridges for Athlons, Pentium III's, and Pentium 4's, then use South bridge chips interchangably.