IBM to embed DRAM in future Power, Cell chips

— 12:17 PM on February 14, 2007

Following presentations from Intel and AMD, it's now IBM's turn to speak about its latest processor design endeavors at the Integrated Solid State Circuits Conference in San Francisco. As EE Times reports, Big Blue doesn't have any 80-core chips to brag about, but it does have plans to embed massive amounts of cache in future processors by using DRAM instead of SRAM. Microprocessors have been using embedded SRAM as cache for years; however, IBM has found a way to migrate DRAM technology to its silicon-on-insulator process. With embedded DRAM, IBM says it can squeeze up to twice as much cache into the same die area.

As a result, the company says it will be able to embed up to 48MB of cache into a "reasonably sized" processor using its 45nm process technology next year. That's a pretty big step up from the company's current Power6 chips, which have 8MB of embedded cache of the SRAM variety. IBM intends to use embedded DRAM in future Power and Cell processors and to make the technology available to its ASIC customers.

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