We've already discussed the new information Intel let slip today about its upcoming Penryn processor, the 45nm die shrink of the Core 2. Penryn chips are expected to enter production late this year. The next step after that is the processor code-named Nehalem. In accordance with the "tick-tock" development rhythm Intel has embraced, Nehalem will also be a 45nm part, but it will bring a major microarchitectural refresh.
Intel's Pat Gelsinger unveiled some basics about Nehalem for the first time today, and in doing so, he called it the first truly dynamically scalable microarchitecture. We don't yet know entirely what that means, but Gelsinger predicted the character of the architecture will become clearer as Intel discloses more about it. Here's what we know about Nehalem now.
In addition, Nehalem will ditch the front-side bus for a series of point-to-point interconnects, presumably similar to AMD's HyperTransport technology.
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