IBM readies new chip-stacking technique


— 3:07 PM on April 12, 2007

Big Blue is preparing chips based on a new interconnect that's designed to vertically link stacked silicon dice, EE Times reports. The interconnect uses connections that are etched through the silicon wafer and filled with metal, a method EE Times says is similar to the way packaged chips are mounted onto a printed circuit board.

According to IBM, the new interconnect shortens data travel distances by a factor of 1,000 while allowing for as many as 100 times more connections. IBM adds that such improvements could help reduce power consumption by 20% in multi-core processors "while increasing the chip's data rate." The interconnect could also help improve power efficiency by up to 40% in silicon germanium-based wireless chips, which would help increase battery life in mobile products. EE Times says the interconnect is more efficient than existing logic and memory chip stacking techniques, which "typically involve intermediate substrates and wiring layers that slow data rates and add complexity."

IBM didn't give the site details regarding its process, but it did state that it was already manufacturing chips based on the "through-silicon via" interconnect, and that it expected to start sending samples to customers in the second half of the year. IBM expects to begin production shipments early next year and to use the technology in Power processors, Blue Gene supercomputer chips, and high-bandwidth memory chips. (Thanks to TR reader Kevin for the tip.)

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