Intel talks 45nm chips, Larrabee at IDF Beijing


— 8:00 PM on April 16, 2007

Today Intel briefed press and analysts on several new products and technologies due to be detailed at the upcoming Beijing Intel Developer Forum, and we have all the dirt. To kick things off, Intel revealed more detailed performance numbers for its upcoming 45nm "Penryn" processors. Intel exec Pat Gelsinger stated last month that Intel had been testing Penryn samples as fast as 3.2GHz. Now, Intel has benchmarked a quad-core Penryn chip running at 3.33GHz with a 1333MHz front-side bus and 12MB of L2 cache. Compared to the existing Core 2 Extreme QX6800, which runs at 2.93GHz with a 1066MHz FSB and 8MB of cache, the 3.33GHz Penryn is reportedly 15% faster in imaging-related applications, 25% faster in 3D rendering apps, more than 40% faster in games, and more than 40% faster with video encoders optimized for Intel's upcoming SSE4 instruction set.

As if such a chip wouldn't be enough for enthusiasts, Intel also announced "Skulltrail," an enthusiast platform that will support up to two quad-core processors and four PCI Express graphics slots. In essence, Skulltrail is Intel's answer to the AMD Quad FX platform, which will presumably be bumped up to dual quad-core processors once AMD finally introduces quad-core chips later this year.

Still keeping with the enthusiast hardware theme, Intel moved on to its "Larrabee project," which is widely expected to be a discrete graphics processor for games. The firm was surprisingly quiet, though, seemingly taking care not to mention games. Instead, Intel stated that Larrabee-based hardware "will include enhancements to accelerate applications such as scientific computing, recognition, mining, synthesis, visualization, financial analytics and health applications." Nonetheless, the company did mention that Larrabee was a highly parallel, Intel Architecture-based programmable architecture, that it would be easily programmable using existing tools, and that it was designed to scale to trillions of floating point operations per second (teraFLOPS).

On the server side of things, Intel announced that quad-core Xeon 7300-series processors with support for multi-processor configurations would arrive next quarter. The chips will be available with 80W and 50W thermal envelopes, and unlike Xeon 5300-series models, they'll support configurations with more than two processors. Intel also officially branded its Geneseo initiative QuickAssist. The initiative is very much like AMD's Torrenza in that it's meant to ease the integration of special-purpose processor accelerators into servers. In Intel's words, QuickAssist "includes support for acceleration using IA-based multi-core processors and third party accelerators working together in Intel-based servers, and developing new integrated accelerators inside the IA-based processor itself." QuickAssist includes a software layer that will allow applications to manage accelerators, too.

Moving along, Intel gave an update on Bearlake, its next generation "3 series" chipset lineup. Bearlake core logic is scheduled to arrive this quarter, and it will bring support for 1333MHz front-side bus speeds, DDR3 memory, PCI Express 2.0, and even Intel's Turbo Memory flash caching system. Versions of Bearlake with integrated graphics will bring hardware DirectX 10 support and "enhanced Intel Clear Video Technology," as well. Intel also says it plans to push its upcoming Santa Rosa platform onto the desktop. "Santa Rosa on Desktop" products will include integrated 802.11n Wi-Fi and support for Turbo Memory, just like Santa Rosa notebooks.

Intel also discussed Tolapai, a family of enterprise-targeted system-on-a-chip (SoC) products that "will integrate several key system components into a single Intel architecture-based processor." Tolapai chips will roll out in 2008, and Intel expects them to reduce chip footprint by up to 45% and power consumption by around 20% compared to "a standard four-chip design." Intel also intends to deliver Intel Architecture-based SoC products in the consumer electronics segment; those chips will pair an Intel architecture-based core with "leading-edge A/V processing, graphics, and more."

Last, but not least, Intel announced that it plans to achieve a ten-fold reduction in power consumption across its processor lineup by the end of this decade, although the company didn't reveal details about how. Intel also intends to keep working on its experimental teraFLOPS-capable 80-core processors, which it boasts can now achieve two teraFLOPS.

   
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