3D silicon integration examined

— 5:06 PM on May 7, 2007

Our friends at Real World Technologies have finished writing up an article about three-dimensional silicon integration. Current chips are single-layered, but according to RWT, researchers at both IBM and Intel have made it clear that stacking multiple layers of transistors is the way to go in the future. The article looks at the main motivations and challenges associated with 3D silicon integration, how the technology works, and what benefits it can provide for modern microprocessors. In the article, RWT examines different 3D bonding techniques, 3D processor design, the impact of 3D integration on yields, and 3D interconnect options including through-silicon vias, which are already being used by both IBM and Samsung.

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