Update: More info on P4 delay

— 11:52 AM on October 3, 2000

Caught this over at The Register. Digit-Life has gotten their hands on a (supposedly) official Intel document detailing the reasoning behind the P4 delay. Check it out:

850/860 chipset erratum identified
- During PCI memory read line or memory read multiple commands, the ICH2 will pre-fetch data from memory and may not invalidate the pre-fetched data(if required), thus allowing invalid data to be delivered to a PCI master
- Issue only occurs in 850/860 chipset based systems due to the unique architectural interactions between the MCH and the ICH2
Silicon fix to tie an existing logic signal in the ICH2 to the buffer invalidate logic

Of course, most of this came out in news yesterday, as you know from my original post. But still an interesting read. You can find The Register's article here, and the post on Digit-Life here.

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