Intel's Common System Interface dissected

— 11:56 AM on August 28, 2007

David Kanter over at Real World Technologies has put together a very thorough article that takes a look at the ins and outs of the Common System Interface, Intel's upcoming answer to the HyperTransport interconnect used by AMD. CSI is expected to appear next year along with Intel's Nehalem processor architecture, which will feature an integrated memory controller just like AMD's current chips.

Kanter's article spares no technical details, and parts of it might be a tad difficult to follow if you're not an electrical engineer. Still, many interesting tidbits about CSI stand out. For instance, Kanter mentions that CSI could be extended from a copper-based parallel implementation to a serial, optical one. There's talk of data speeds, too: initial implementations of CSI are expected to provide 12-16GB/s of bandwidth in each direction, or 24-32GB/s of bandwidth per link. For reference, next-gen HyperTransport 3.0 links top out at 20.8GB/s of full-duplex bandwidth, and Intel's 1333MHz front-side bus peaks at 10.7GB/s.

Kanter also speculates on Intel's future CSI implementations. In the desktop and mobile spaces, he doesn't expect the interconnect to have a huge impact. However, he thinks CSI will be key to helping Intel win back market share from AMD in the server space.

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