AMD tricks out Mustang
To better compete with Intel's upcoming Pentium 4 chip, AMD is prepping a revised Athlon, code-named Mustang. We've known for a while the Mustang would include large amounts of on-chip L2 cache memory, but now some details about architectural tweaks to the Athlon core are emerging. I saw at JC's House o' Hooch that the Germn mag c't has details on hardware prefetch logic being built into the Mustang. What's that mean? I'm just gonna rip JC's explanation of prefetching now, since it's late and JC already did a fine job:
Prefetching effectively decreases the average latency to memory, as it tries to predict which memory blocks will be requested in the future, and tells the system to put those blocks into cache in anticipation of these requests, not unlike how a branch predictor speculates on which instructions will be requested by the cpu
In other words, the processor will be able to keep itself better fed by guessing about which bits to grab from main memory and store in the cache. Since the Mustang's supposed to have a honkin' cache the begin with, this method may prove wickedly effective. Combine that all with DDR SDRAM (which has twice the bandwidth of current systems), dual-processor support, and maybe some Micron mamba action
, and this 'stang will flat-out run.
By the way, that c't link points to a translator, since the original's in German. So when you read about "Intels mobile parliamentary group", don't freak. Far as I know, all parlimentary groups are heavy, poorly coordinated, and slow-moving. With any luck, they'll stay that way.