Intel Silverthorne mobile chip to be slower than expected?


by Cyril Kowaliski — 5:17 PM on December 12, 2007

At Computex this summer, Intel revealed more details about its strategy for "mobile Internet devices" (MIDs) and Menlow, the successor to its McCaslin MID platform. Unlike McCaslin, Menlow will include a new processor designed to compete head-on with the non-x86 chips that currently dominate the handheld industry. That processor is dubbed Silverthorne, and we already know it's an x86 part based on 45nm process technology, but Intel hasn't talked much about the architecture behind it.

Luckily, the folks at Ars Technica—with the help of David Kanter from Real World Technologies—were able to unearth some additional information about Silverthorne's design in the program for the 2008 International Solid State Circuits Conference. The information says Silverthorne will have a two-issue, in-order pipeline with integer and floating point execution units, 32KB of iL1 cache, 24KB of dL1 cache, 512KB of L2 cache, and a 533MT/s front-side bus.

According to Ars, that suggests the chip harbors a design similar to that of the original Pentium processor, which was also a two-issue, in-order chip. Based on this find, the site extrapolates that Silverthorne will be at a performance and power efficiency disadvantage compared to RISC embedded processors from the likes of ARM: "I think we can safely assume at this point that Silverthorne will be clock-for-clock slower and less efficient than a comparable ARM part, especially on integer-intensive Web and productivity apps." Instead, Intel will have to rely on its process technology advantage to stay competitive, with 45nm Silverthornes set to fight it out against 65nm ARM chips.

   
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