Thanks to those of you who wrote in with suggestions for the Friday Night Topic. Unfortunately, I dropped the ball on getting one posted—forgot I had to head out early in the evening to a school orientation thing for my kids. Also, I suppose the FNT is a pretty old-school feature around here, so I should make something clear: on Friday nights, our topic of discussion is typically intended to be outside the realm of what we usually cover. Quite a few of you suggested we talk about this or that area of technology, which made topic selection tough.
Anyhow, it's still my fault for not getting a topic posted. Apologies for that.
To make up for it, I'll post one of the tech-related topics here for us to kick around. Saurav writes:
A pet peeve of mine is the proliferation of x86 based CPUs like the Atom into every niche of the microprocessor market. I believe that system-on-a-chip solutions with RISC cores like the TI OMAP (Palm Pre) offer better performance per dollar and performance per watt in netbook/smartphone like applications. Personally, I feel that the only reason x86 is becoming so popular is Intel's clout and a collective obsession with backwards compatibility.
I believe the question is whether x86 compatibility is worth the overhead required to translate x86 instructions into the RISC-like internal micro-ops most x86 cores actually execute. This debate has played out over time with a pretty decisive answer in favor of x86 in the desktop, workstation, and server markets, but the power and size constraints of cell phones have left the door open for competitors like ARM. Heck, ARM and ARM-derived processors currently dominate in smart phones. Should x86-compatible processors succeed in smart phones, netbooks, and other mobile devices, or would users be better served by other alternatives?
I saw Dirk Meyer speak at VTF some years ago, and he argued that only 2% of Opteron die area was dedicated to "x86 overhead." In fact, let me quote my report at some length:
Meyer opened by recounting AMD's experience in developing the AMD64 extensions to the x86 instruction set, then turned to a series of bold predictions about the coming success of x86 and AMD64. He claimed AMD64 will be the standard for both computing and personal electronics, then backed it up with an unequivocal statement: "the x86 architecture is the only architecture the world will ever need." Meyer elaborated by arguing that ISA innovation is not necessary for better performance, lower costs, or lower power consumption.
To back up this claim, he showed a slide containing a microphoto of an Opteron die with various die areas highlighted. About 40% of the chip area was L2 cache, 25% was the I/O ring, 10% was L1 cache, 9% the north bridge and HyperTransport, under 10% was ALUs, and 2% was branch prediction units. About 2% was dedicated to what he called "x86 overhead." In other words, he said, ISAs don't take up much area, so "let's quit screwing around with them."
Meyer recounted the deaths of a number of ISAs in the past five to ten years, then said that IBM's Power architecture will die in a few years and be gone by the end of the decade. He predicted future investment and microarchitectural innovation will happen around the x86 ISA, and noted the wide range of design choices open to processor engineers, from short pipelines to long, low frequency to high, and the like.
Given these things, Meyer predicted x86 will be the basis for a wide range of future devices, from storage to networking to consumer and personal electronics. Perhaps most surprisingly, Meyer's comments seemed to be almost wholly uncontroversial to his audience at VTF.
So there's that. Of course, this is AMD speaking. At a Via event, no less.
But Meyer seems to have been on to something. Intel's Atom architecture has made some of his predictions about the range of choices designers of future x86 chips might make (see the slide in my original post) come true. This low-power, in-order design with a tiny die size is Intel's first crack at an x86 CPU for smaller devices, and the Atom is slated to shrink from here.
Not only that, but the Atom's architects pointed out to us that 96% of all x86 instructions in typical workloads are executed on the Atom as single-micro-ops. The majority of the rest are actually fused from multiple x86 instructions into single Atom uops. Yes, some complex x86 instructions must be handled via microcode still, but they make up a vanishingly small percentage of typical workloads. The preponderance of 1:1 translation means the Atom's x86 compatibility should require very little overhead in everyday use. Atom's architects claimed doing things this way gives the chip a higher IPC and better power efficiency than translating x86 instructions to more, simpler uops.
The big players in x86 microprocessors seem to be saying two things: that endowing a CPU with x86 compatibility isn't an especially daunting problem, and that problem may have been solved already in a way that accounts nicely for power efficiency. Intel still has a ways to go until the Atom fits into ARM-like power envelopes, but would you bet against them because of the overhead required to support the x86 ISA? Discuss.
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