Three months ago, Intel revealed a good number of details about its upcoming Nehalem-EX server processor. We learned about the CPU's eight cores, 16 threads, 24MB L3 cache, quad memory channels, eight-socket support, and Itanium-derived reliability features.
Fresh from the Hot Chips 21 conference, where Intel disclosed new details, Charlie Demerjian from SemiAccurate has written up an article that delves more deeply into Nehalem-EX's cache architecture, system interface, and QuickPath controller design.
Demerjian points out that the 2.3-billion-transistor behemoth is much more than a pair of quad-core Nehalem dice glued together. Rather sharing the 24MB L3 cache between all eight cores, for instance, Intel chopped it up into eight 3MB "slices." Each slice belongs to a core, but it can talk to the other slices thanks to a bi-directional ring bus and some sophisticated synchronization features. (Those features involve reversing polarities, so Star Trek fans will feel right at home.)
Reportedly, the ring "has four times the bandwidth of a similar width unidirectional ring, half the latency, and never sends anything that the receiver can't read." Total raw bandwidth: 250GB/s. Not bad. Also, at the heart of the CPU, Intel has added a central crossbar switch that takes care of shuffling data between "all internal and external channels, up to eight at a time." Check out the full article for more details.
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