PCIe 3.0 blamed for Sandy Bridge E delay


— 11:48 AM on September 9, 2011

Every motherboard maker we talked to at Computex earlier this summer told us to expect X79-based mobos designed for "Sandy Bridge E" processors right about now. I'll let you in on a little secret: I'm not frantically testing a stack of X79 boards ahead of an imminent launch. Intel's new high-end platform appears to be delayed, and Charlie Demerjian over at SemiAccurate thinks he knows why. The problem, according to Demerjian's sources, is the physical interface (PHY) associated with PCI Express 3.0. The PHY is needed to pass PCIe signals outside the CPU, and it's reportedly only comfortable running at PCIe 2.0 speeds.

Third-generation PCI Express connectivity is built into the Sandy Bridge E CPU, where it will fuel expansion slots in addition to underpinning the DMI interconnect linking the processor to its accompanying X79 chipset. Problems with the associated PHY could not only slow communications with graphics cards, but also cap the bandwidth between the CPU and the chipset. Neither is a particularly appealing prospect for a new flagship platform targeted at servers, workstations, and multi-GPU enthusiasts.

SemiAccurate says the PHY needs to be respun, and the new revision won't be ready until next year. We could still see Sandy Bridge E debut before then, but it may not do so with its PCIe 3.0 connectivity intact.

   
Register
Tip: You can use the A/Z keys to walk threads.
View options

This discussion is now closed.