Haswell to offer new extensions for transactional synchronization


— 1:07 PM on February 9, 2012

Ivy Bridge isn't yet out the door, but Intel is already talking about more enhancements coming in Haswell. The next-generation chip will bring a new microarchitecture and, according to this blog post, a set of Transactional Synchronization Extensions dubbed TSX. The instructions are designed to simplify programming for developers working on multithreaded applications, which must lock sections of memory to ensure that data being manipulated by one thread isn't modified by another. Intel's James Reinders explains:

These extensions can help achieve the performance of fine-grain locking while using coarser grain locks. These extensions can also allow locks around critical sections while avoiding unnecessary serializations. If multiple threads execute critical sections protected by the same lock but they do not perform any conflicting operations on each other’s data, then the threads can execute concurrently and without serialization. Even though the software uses lock acquisition operations on a common lock, the hardware is allowed to recognize this, elide the lock, and execute the critical sections on the two threads without requiring any communication through the lock if such communication was dynamically unnecessary.

Reinders goes into more detail in a subsequent blog post. I'm not a programmer, but it looks like Haswell is capable of determining when it's safe for incoming threads to ignore the locks imposed by other threads. This should allow more threads to be executed in parallel, at least for applications relying on coarse locking techniques. Coarse locking is easier to implement than fine-grained locks, Intel says.

Applications will have to be modified to take advantage of TSX. Two options are available: developers who want to retain compatibility with non-TSX hardware can use the Hardware Lock Elision instruction set, while those who want more flexibility can use the Restricted Transactional Memory instruction set. The latter requires an alternate code path for hardware that doesn't support TSX instructions. If you want more information on TSX, check out chapter 8 of Intel's programming reference (PDF).

   
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