Papermaster details new AMD mobile, server roadmaps


— 1:50 PM on June 14, 2012

AFDS — At the closing keynote of the Fusion Developer Summit in Bellevue, Washington today, AMD Executive VP and CTO Mark Papermaster gave us a glimpse of AMD's latest roadmaps for its 2013 mobile APUs and server CPUs.

AMD has three APUs in the pipeline for next year—all of which Papermaster says will deliver "no-compromise solutions" for tablets and fanless notebooks. At the high end, Kaveri will deliver four cores based on AMD's Steamroller architecture (the successor to Bulldozer and Piledriver) and integrated Radeon HD graphics. Papermaster said Kaveri will be the first AMD APU with fully shared memory and virtual shared memory. AMD expects Kaveri to fit into 15-35W thermal envelopes and to populate 13.3-15.6" notebooks with thicknesses of 0.83" or less.

For cheaper and lower-power applications, AMD is prepping Kabini, the successor to today's Zacate and Ontario APUs. Kabini will feature four Jaguar cores (Jaguar being, of course, the successor to Bobcat), Radeon HD integrated graphics, and power envelopes in the 9-25W range. Kabini-based notebooks should have 11.6-15.6" screen sizes and thicknesses in the vicinity of 0.71-0.94".

Last, but not least, will be AMD's next-gen APU for tablets: Temash. Like Kabini, Temash will feature four Jaguar cores and integrated Radeon HD graphics. However, it will squeeze into thermal envelopes as slim as 3.6W. AMD says Temash will power 10-11" tablets as thin as 0.39".

On the server front, AMD plans to launch the Abu Dhabi, Seoul, and Delhi CPUs later this year. These chips will succeed Interlagos, Valencia, and Zurich, respectively, fitting into the same G34, C32, and AM3+ sockets. The memory configurations will remain the same, as will core counts. From what I can tell, the only difference will be a substitution of Bulldozer cores for Piledriver ones. (Piledriver is currently found in AMD's Trinity APUs, but existing Opterons are still Bulldozer-based.)

Papermaster also communicated a desire for AMD to be more agile and to get new solutions to market more quickly. He brought up yesterday's announcement about ARM's TrustZone security IP finding its way into future AMD silicon. Speaking more broadly, Papermaster said AMD's strategy involves "flexibility around ISA." ISA stands for Instruction Set Architecture, so this might hint at even deeper collaboration with ARM—like, say, coupling ARM CPU cores and Radeon graphics without an x86 CPU. Considering that ARM is espousing AMD's Heterogeneous Systems Architecture and backing AMD's HSA Foundation, such a combination doesn't seem unlikely.

   
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