Leak slides spill Haswell chipset details


— 11:18 AM on November 12, 2012

Intel's next-generation Haswell CPU is due out next year, and details are trickling out about its supporting Lynx Point chipset. According to a series of slides posted at Chinese site EXPreview, desktop-bound versions of the platform will sport six USB 3.0 ports, 14 USB 2.0 ports, six 6Gbps SATA ports, and eight PCIe 2.0 lanes. Two of the USB 3.0 and 6Gbps SATA ports are listed as "muxed with PCIe," suggesting some bandwidth sharing with the PCI Express lanes. It's still nice to see additional high-bandwidth I/O ports, though.

Some of those ports will purportedly disappear in Lynx Point-LP, a low-power version of the chip targeted at mobile systems. USB connectivity is cut to eight 2.0 ports and four 3.0 ones. Only four SATA ports remain, and just three of them can hit 6Gbps speeds. The number of PCIe lanes has been trimmed to six, as well. Interestingly, all the SATA ports and two of the USB 3.0 ports are apparently being handled through the chipset's PCI Express interface.

CPU overclocking support appears to have been dropped from Lynx Point-LP, which isn't surprising. What's really interesting is the omission of the DMI and FDI interconnects that usually hook up to the CPU. In their place, Lynx Point-LP will reportedly use a new OPI link with eight lanes of bandwidth. OPI stands for On Package Interface, and one of the slides shows the platform hub sitting on the same package as the Haswell CPU. Oooh.

Lynx Point will be fabbed on a 32-nm process, say the slides, so it shouldn't take up too much room on the package. It appears the chipset will be part of the CPU's thermal management scheme, with CPU throttling invoked if the platform hub gets too hot, and vice versa. To further conserve power, it looks like ultra-low-power versions of Haswell will be able to drop their base clocks from 100MHz down to just 24MHz. These so-called ULT chips will additional support C8, C9, and C10 power states that will be absent from the desktop line.

Haswell was designed primarily for thin-and-light mobile systems, so a greater degree of platform integration only makes sense. Given Intel's history of moving platform components onto the chip package before integrating them into the die, I wonder if Haswell might be the last Intel microarchitecture without SoC-style integrated I/O.

   
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