LSI SandForce details next-gen error correction technologies


— 8:00 AM on August 13, 2013

At the Flash Memory Summit in Santa Clara, California this week, LSI SandForce is providing an early glimpse at the error correction mojo that will be part of its next-generation SSD controller. Dubbed SHIELD, this collection of technologies is designed to extend the useful life of NAND built on smaller lithography processes. Flash makers pursue smaller cell geometries to lower the cost per gigabyte, but that shrinkage also makes the NAND more prone to errors. To mitigate the impact of those errors, SHIELD employs multiple levels of error correction.

The first level of error correction is a "hard" low-density parity check that's applied to every read request. This HLDPC layer doesn't impact performance, but it's also not perfect. To address errors that slip through the cracks, HLDPC is backed by five levels of "soft" LDPC. These additional levels employ advanced noise handling and signal processing techniques designed with the NAND's analog characteristics in mind. Each level adds a little more latency to the equation, though. 

Source: LSI

SHIELD's last line of defense is RAISE, the RAID-like redundancy scheme available with current-gen SandForce controllers. Correcting errors with RAISE adds about 10 milliseconds of latency, according to LSI, so the scheme is used sparingly. To ensure optimal performance, SHIELD only invokes stronger levels of error correction when necessary. The decision-making intelligence involved requires some additional computational horsepower, but LSI isn't ready to divulge details on that front. We can, however, tell you that the new controller has parallel LDPC engines with "specialized hardware." 

Source: LSI

Another component of SHIELD adjusts the number of bits used to store the ECC data associated with each flash page. This so-called adaptive code rate allows the controller to dedicate more bits to ECC as the flash erodes and becomes more error-prone. When the flash is fresh and requires little error correction, those bits are devoted to overprovisioned spare area to boost performance. As write-erase cycles accumulate, more bits are are used for ECC to squeeze more life out of the NAND.

Interestingly, LSI says SHIELD also tracks some previously read data. That data can then be used to speed the recovery time for future errors. Sounds like some sort of caching may be involved there, though we don't know for sure. LSI doesn't plan to discuss other elements of its upcoming SSD controller until the fourth quarter of this year. We're told the chip will be sampling to LSI's customers in the third quarter, so drives based on the chip could debut before the end of the year.

Although SHIELD won't trickle down to the SandForce controllers found in existing SSDs, those chips are compatible with a new feature called DuraWrite Virtual Capacity (DVC). SandForce's DuraWrite tech compresses host writes to reduce their flash footprint. Normally, the space saved is treated as overprovisioned spare area, which can then be tapped to improve performance. With DVC, that storage is effectively passed along to the user as additional drive capacity, making it possible to store more data than the drive's stated capacity.

DVC is handled in the firmware, but it might not be possible to flash an existing drive to take advantage of the feature. Some firmware elements are hard-coded and can't be changed. In any case, LSI says operating-system support is the biggest hurdle to DVC adoption. Windows doesn't support dynamic drive capacities, so DVC can't extend an SSD's capacity with the operating system. LSI expects Linux to take advantage of the tech quickly. It also plans to deploy DVC in an enterprise-oriented Nytro accelerator drive in the "not too distant future." That caching solution won't expose the size of the drive to the operating system, so compatibility shouldn't be an issue.

   
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