Imagination Technologies has introduced the first CPU core of the MIPS Series5 "Warrior" lineup it announced in June. The P5600 is a 32-bit core aimed at low-power mobile and embedded devices. Thanks to the MIPS Release 5 ISA, this core supports 128-bit SIMD computation and hardware-assisted virtualization. This new MIPS ISA also allows for 64-bit instructions, as a superset of the 32-bit execution path, but this particular core doesn't support the extra bits.
Still, the P5600 can access up to a terabyte of memory via virtual addressing. The mobile devices Imagination Tech is targeting won't have nearly that much memory, but the company notes that the CPU can also be used for networking applications and microservers that may demand more memory than the average smartphone or tablet.
Imagination has designed the P5600 to participate in a CPU cluster that combines up to six cores behind a "coherence manager" that packs up to 8MB of L2 cache. When built using the high-performance mobile variant of TSMC's 28-nm fabrication process, the individual cores can apparently scale up to 2GHz. Imagination Tech doesn't quote power figures, but it says the P5600 offers "industry-leading single thread performance ... at significantly lower power than its competitors."
Imagination Technologies is best known for producing the PowerVR graphics technology used in Apple's SoCs. Those chips feature CPU cores compatible with the ARM instruction set, which is much more popular than MIPS, at least in the mobile world. With AMD working on ARM-based chips, Qualcomm and Nvidia both firmly entrenched in the ARM camp, and Intel bringing x86-compatible processors to the mobile market, it will be interesting to see what's left for MIPS-based CPUs like the P5600.
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