Leak suggests PCIe 3.0 coming to next-gen Intel chipsets


— 9:27 AM on July 15, 2014

For years, Intel's core-logic chipsets have been limited to Gen2 PCIe. The older interface persisted even as the firm's CPUs adopted faster Gen3 lanes. However, the latest leak suggests the next generation of chipsets will finally join the party. VR Zone's Chinese site has posted a series of official-looking slides indicating that next year's "100 Series" chipsets will support PCI Express 3.0.

According to the slides, the flagship member of the family will be the Z170, which reportedly has up to 20 lanes of PCIe Gen3 connectivity. That sounds like an awful lot, but I count only six lanes reserved exclusively for PCIe slots and devices. Most of the lanes appear to be shared with the chipset's USB, SATA, and Ethernet interfaces.

Those other interfaces are apparently getting a boost, as well. The slides show the Z170 with up to three PCIe storage ports, three SATA Express ports, and 10 USB 3.0 ports. Each PCIe storage link can have up to four lanes, while the SATAe connectivity is limited to two. All of those storage links will evidently be covered by Intel's RST drivers. The standard PCIe lanes should also support storage devices, but software support will probably have to come from the OS or third-party drivers.

Like previous Intel chipset families, the 100 Series includes multiple variants, each one with a different subset of the flagship's features. It looks like the actual chip has 26 high-speed I/O lanes that can be reconfigured and disabled selectively. Six of those lanes are shown as USB-only, while the remainder can be assigned to PCIe, SATA, or LAN duty. The arrangement looks pretty slick—and perfectly suited to Intel's M.O. of using a single chip to underpin a range of different products.

   
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