SemiWiki, otherwise known as the Semiconductor Wiki Project, has pulled together some interesting data on the feature density of competing fabrication nodes from the world's biggest chip makers. The information details the actual gate and metal pitch of each process starting at 130 nm. There's data on future 10-nm tech, too, though much of it is extrapolated from historical trajectories.
As the article explains, the singular nanometer figure typically used to describe fabrication processes doesn't necessarily give an accurate depiction of feature sizes. SemiWiki breaks things down using an Intel metric that multiplies the gate pitch by the "metal 1" pitch. As I understand it, the gate pitch refers to the distance between logic gates, while the metal 1 pitch describes the thickness of the lowest (and thinnest) layer of interconnects.
According to the data, the density crown was passed back and forth between TSMC and Intel during the 130-65-nm era. From 45-20 nm, GlobalFoundries and Samsung (which share a common platform alliance) claimed the highest density. The 14/16-nm node belongs to Intel, though, and SemiWiki projects that the firm will maintain its lead with the 10-nm node after that.
Although the "GP x M1P" metric is billed as a good measure of "pure process density," SemiWiki adds that the figure may not be representative of how tightly features are packed into actual products. The numbers are still interesting, though—especially for folks who want to argue about chip-making prowess on the Internet.
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