Intel slides detail Skylake microarchitecture, energy efficiency features

— 2:13 PM on August 18, 2015

IDF - Intel is presenting the details of the Skylake microarchitecture at IDF today. There's no live stream of the presentation, but a PDF of the slide deck illustrating the new chip's innards has leaked been made available. The company has also released another, more detailed slide deck with information about the chip's power management features and efficiency, among other things. Go get copies while you can: we can't guarantee how long these will be publicly accessible.

Scott is at IDF, and he's tweeting the highlights. Some of the juicy details so far: Skylake chips can power off their AVX2 hardware when it's not in use. The new chip's ring fabric has two times the bandwidth of Broadwell chips at the same level of power consumption. Intel has significantly overhauled the eDRAM cache architecture in Skylake chips, and that memory can even be used to transfer data between I/O devices now. Perhaps the most impressive figure yet is the fact that the Skylake front-end can pull six instructions per clock out of its μop cache.

Follow Scott on Twitter for more highlights as IDF continues.

Updated 8/18/2015 at 3:30 PM to add more Intel slides and more precise language.

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