When we last checked in with Soft Machines about a year ago, the company had just announced its VISC CPU architecture, along with some surprising performance claims. Today, the company presented some more details about the VISC architecture, along with a roadmap for VISC CPUs and SoCs, at the 2015 Linley Processor Conference. We spoke with Soft Machines founder and CTO Mohammad Abdallah and the company's VP of marketing and business development, Mark Casey, to learn more about these chips.
The VISC architecture
VISC CPUs are built around the concept of "virtual cores" and "virtual hardware threads." A middleware layer sits between the guest operating system and its targeted instruction set architecture. This middleware translates the guest application's ISA into VISC's native instruction set and distributes its workload across the CPU's virtual cores.
The most fascinating aspect of VISC is that even in single-threaded workloads, the underlying hardware has the ability to divide that work into chunks that Soft Machines calls "threadlets." In turn, a VISC CPU can distribute the work of a demanding single thread on a virtual core across multiple hardware cores. It can also dynamically provision computing resources in mixed workloads where a demanding thread and a lighter-weight task need simultaneous access to CPU resources. That flexible resource allocation purports to allow VISC to deliver two to three times the instructions per clock of traditional CPUs.
The virtual core concept is also key to another one of VISC's claimed aces in the hole: power scaling. Traditionally, CPUs rely in part on increasing clock frequency to improve performance, and increasing frequency requires lots of power. Overclockers will already be familiar with the huge role that voltage increases play in power consumption and heat generation. This power wall is one of the major limits to increases in CPU clock speed—and to some extent, performance—of late.
VISC may perform an end-run around this power wall to some degree, since it can ideally muster unused computing resources from idle hardware cores and bring them to bear on a gnarly task executing on a single virtual core. Since the VISC CPU gets its performance gains from scaling resources rather than frequency, its power scaling characteristics are supposed to be more linear than a traditional CPU with dynamic voltage and frequency scaling, whose power expenditures follow the dreaded exponential curve as load increases. These power savings are claimed to allow VISC CPUs to deliver up to four times the performance per watt of competing chips.
Soft Machines won't produce VISC CPUs on its own. Instead, the company hopes to license its intellectual property to partners, much like ARM and Imagination Technologies do. It'll also work with partners to tailor VISC chips to their own applications.
The first commercial VISC CPU design, code-named Shasta, can present one or two virtual cores to the guest operating system on top of two physical cores with 1MB of L2 cache each. Shasta is a 64-bit CPU, and because of the VISC translation layer, it can run applications built for a number of other ISAs. Most critically, Soft Machines says it's been able to scale frequencies from 500MHz in its 28nm prototype CPU to 2GHz with Shasta. That's thanks in part to targeting a 16nm FinFET process. The chip has a built-in, generic 256-bit interconnect bus that's adaptable to customers' own interconnect specifications. Shasta can also be configured in symmetric multi-processor configurations using Soft Machines' proprietary coherency tech.
Because of its power-scaling characteristics, Soft Machines says the Shasta CPU can deliver "server performance at mobile power." According to its own testing with the SPEC2006 benchmark, the company says a Shasta CPU can deliver higher performance in similar power envelopes when compared to a number of competing CPU cores ranging from mobile to desktop designs.
Soft Machines is also developing an SoC based on the Shasta CPU, which it's calling Mojave. This chip can scale across a number of power targets, from "high-end Internet of Things" devices to servers. Mojave is built around two dual-core Shasta processors to start with, while the rest of the SoC is meant to be easily customizable by design partners.
Some potential IP blocks on Mojave include one to four channels of low-power or regular DDR4 memory running at anywhere from 2400 to 3200MT/s, one to 8MB of system cache, display and imaging blocks with up to three 4K-capable display outputs, and inputs for dual 20MP cameras. The company says it's also working with Imagination Technologies to integrate the graphics firm's next-generation graphics-processing IP with the Mojave SoC, and the two companies are working to coordinate their roadmaps to hit a mid-2016 tapeout.
According to Soft Machines, the first partner products based on VISC CPUs will be announced in mid-2016. The company's roadmap will include parallel development of VISC CPUs and SoCs. The company's Shasta+ core IP will feature one to four virtual cores when it arrives in 2017, and it'll target the 10-nm process node once it hits production later on. The accompanying Tabernas SoC, much like Mojave, will incorporate Shasta+ cores in an SMP design. The Tahoe CPU will include anywhere from one to eight VCs on the same 10-nm node when its IP arrives in 2018.
We're fascinated by Soft Machines' technology, and it'll be interesting to see whether shipping hardware can deliver on the company's performance claims. If VISC works as claimed, certain parts of the CPU marketplace could be about to heat up. We'll be keeping an eye out for more details of VISC CPUs as they become available.
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