We've heard some pretty impressive performance claims about the A9X SoC in Apple's iPad Pro ever since the mega-slate made its public debut, and now we know a little more about the hardware that makes it all happen (even if it isn't quite surpassing x86 PCs just yet). Reverse-engineering firm Chipworks has teamed up with Anandtech to examine the guts of the A9X, and they've drawn some interesting conclusions looking at the floor plan of the 147-mm2 die.
Apple's SoCs are well-known for using two strong custom CPU cores, and the A9X doesn't depart from tradition in that regard. What is surprising is the large amount of chip area given over to graphics processing on the A9X. Anandtech believes that Apple has crammed 12 PowerVR Series7 GPU "clusters" onto this chip, and to solve the problem of feeding them, the company has apparently implemented a 128-bit LPDDR4 memory subsystem, good for 51 GB/s of memory bandwidth. That figure doubles the A9 SoC's memory bandwidth, according to Anandtech's figures.
The biggest surprise Chipworks and Anandtech found is that the A9X doesn't have an L3 cache. Past Apple tablet SoCs have included this cache, but Anandtech guesses that its absence on this latest chip is in part because of the added memory bandwidth from the move to LPDDR4, and in part because of the iPad Pro's less-constrained thermal envelope. The site thinks that the A9X can afford to perform power-intensive memory operations that the more thermally-constrained (and L3-cache-equipped) A9 SoC in iPhones can't, making a third level of cache unnecessary. Anandtech further speculates that because of the removal of the L3 cache, the amount of L2 cache for those GPU cores may be greater than on the A9 SoC, too.
Unlike the controversially dual-sourced A9 SoC, Anandtech and Chipworks say there's no reason to believe the lower-volume A9X is dual-sourced, too. Chipworks believes that Apple is sourcing the A9X exclusively from TSMC and that the chip is fabricated on that foundry's 16-nm FinFET process.
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