Intel subsidiary Altera has launched the Stratix 10 field-programmable gate array (FPGA). The Stratix 10 comprises 5.5 million logic elements, HBM2 memory, and a quad-core ARM Cortex-A53 processor. Those components are joined together using what Altera dubs Heterogeneous 3D System-in-Package (SiP) integration. The upshot of this stack of acronyms is up to 10 TFLOPS of single-precision output and 10 Tbps of local memory bandwidth to go along with up to 30 Gbps of chip-to-chip capacity.
The new chips are built on Intel's 14-nm FinFET (Tri-Gate) fabrication process. Altera claims a doubling of performance or a 70% power reduction at equivalent performance level when compared to previous-generation products. An integrated Secure Device Manager block ensures the integrity and security of data. The Stratix 10's main job is to ultimately act as a coprocessor within a more conventional server, as the ARM CPU's job is to provide memory management and other services to the FPGA.
Like modern GPUs, FPGAs excel in execution of extremely parallel workloads, but with near-ASIC levels of application specificity. The FPGA's primary advantage over an ASIC (application-specific integrated c is that an FPGA's logic units can be reconfigured at a programmer's whim.
Altera says the Stratix 10 should be software-compatible with previous-generation Arris FPGA chips. Bing researchers at Microsoft are surely very excited about the promises of increased efficiency. The Stratix 10 is now sampling to "select customers."
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