As process nodes become smaller and smaller, chip manufacturers have to work harder to squeeze performance and power savings out of each step. To wit, Intel's recently changed from its familiar "tick-tock" cadence of alternating die-shrinks and architecture updates to a three-step "process-architecture-optimaztion" model. Likewise, Samsung's fabrication arm recently presented the latest revisions of its 10-nm and 14-nm process nodes to its manufacturing partners at its Device Solutions America headquarters.
Samsung showed off the latest version of its 14-nm process, the company's fourth generation at that node size. The new fabrication technology, dubbed 14LPU, is intended for "high-performance and compute-intensive applications" and will deliver "higher performance at the same power and design rules."
The new 10-nm process, which Samsung calls 10LPU, is the company's third go-round with fabrication at that node size. Samsung claims the new process will allow for smaller die sizes compared to its older 10-nm offerings. Samsung goes on to claim that 10LPU could be "the most cost-effective cutting-edge process technology in the industry."
Refinements at existing node sizes are great, but smaller sizes are probably more interesting to readers. Samsung took the opportunity to show off 7-nm EUV wafers and provide updates on this process to its partners.
Samsung says process design kits for the 14LPU and 10LPU processes will be available in the second quarter of next year. We expect that actual products built with these technologies will appear not too long after that.
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