Some things are better late than never. At its yearly developers conference, PCI-SIG announced the PCI Express 4.0 specification to its members. As expected, the updated I/O technology will offer twice the bandwidth of PCIe 3.x while retaining full backwards compatibility.
Although it started as a key I/O component in PCs, PCIe now serves as the interconnect for any number of devices, including those in the server, storage, and mobile markets. The full details of the new specification haven't yet been published on the consortium's website, but we're told that it doubles the per-pin bandwidth of the previous generation, offering 16 GT/s data rates.
Given PCIe's wide variety of use cases, PCI-SIG also decided to improve the interconnect's flexibility and scalability. Developers will have access to more lane width configurations and speeds suitable for low-power applications. Other enhancements include reductions to system latency, improved scalability for added lanes, and lane margining.
PCI-SIG also teased the upcoming PCIe 5.0 specification. Penciled in for 2019, PCIe 5.0 will push the available bandwidth to 32 GT/s. One application that the consortium has in mind is high-end networking, where the architecture can serve up 128 GB/s of bandwidth operating at full duplex.
The PCIe 4.0 specification still needs to undergo a final IP review, but the PCI-SIG claims that the interconnect is ready to go. Prior to the publication of the spec, the SIG had already been doing compliance testing with a variety of its members, and it claims that a number of 16 GT/s solutions have already been worked out. Perhaps we'll see products using the new spec make their way to shelves sooner than later.
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