Chipmakers adjust to new realities

— 11:07 AM on January 20, 2004

EETimes has an interesting article up about the challenges semiconductor manufacturers are facing as transitions to smaller process technologies become increasingly difficult. The occasion for the article is a speech given by Bernard S. Meyerson, CTO of IBM Microelectronics, but he's addressing concerns felt industry-wide.

The audience keenly listened as Meyerson told how a dramatic rise in power density, brought about by the traditional brute scaling of process technology dictated by Moore's Law, has already yielded silicon that could iron a pair of pants and is on a curve heading toward supernova.

In other words, physics is getting ugly. The days of relatively generous amounts of gate oxides, on the order of say 30 angstroms, have given way to the angst of dealing with less than 10 angstroms, making brute scaling nearly impossible. That's why some in the industry, including Meyerson, believe that classical CMOS scaling is no longer possible.

The article suggests that design-level innovations may have to replace die shrinks as the big scheduled changes on chipmakers' roadmaps. There's also talk about the need for closer collaboration between design engineers and process engineers, which may be especially dicey for fabless semiconductor companies with aggressive schedules, like ATI and NVIDIA.
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