More Cell processor details emerge

— 11:28 AM on November 29, 2004

EE Times has unearthed some new details on IBM, Sony, and Toshiba's upcoming Cell processor. Here's a snippet to whet your appetite:

Each processing element comprises a Power-architecture 64-bit RISC CPU, a highly sophisticated direct-memory access controller and up to eight identical streaming processors. The Power CPU, DMA engine and streaming processors all reside on a very fast local bus. And each processing element is connected to its neighbors in the cell by high-speed "highways." Designed by Rambus Inc. with a team from Stanford University, these highways — or parallel bundles of serial I/O links — operate at 6.4 GHz per link. One of the ISSCC papers describes the link characteristics, as well as the difficulties of developing high-speed analog transceiver circuits in SOI technology.
Sony's estimates that each Cell processor has a performance potential of one teraflop, although given the chip's complex design, real world performance may not measure up to theoretical peaks.
Tip: You can use the A/Z keys to walk threads.
View options

This discussion is now closed.