AMD, IBM develop new strained silicon technique

— 11:57 PM on December 12, 2004

The collaboration between AMD and IBM on new chip manufacturing technology has produced its first big development, or so sayeth the press release:

SUNNYVALE, CA and EAST FISHKILL, NY-December 13, 2004-AMD and IBM today announced that they have developed a new and unique strained silicon transistor technology aimed at improving processor performance and power efficiency. The breakthrough process results in up to a 24 percent transistor speed increase, at the same power levels, compared to similar transistors produced without the technology.

Faster, more power-efficient transistors are the building blocks of higher performance, lower power processors. As transistors get smaller, they operate faster, but also risk operating at higher power and heat levels due to electrical leakage or inefficient switching. AMD and IBM's jointly developed strained silicon helps overcome these challenges. In addition, this process makes AMD and IBM the first companies to introduce strained silicon that works with silicon-on-insulator (SOI) technology, resulting in an additive performance and power savings benefit.

Sounds good so far. There's more detail in later in the release:
The new strained silicon process, called "Dual Stress Liner," enhances the performance of both types of semiconductor transistors, called n-channel and p-channel transistors, by stretching silicon atoms in one transistor and compressing them in the other. The dual stress liner technique works without the introduction of challenging, costly new production techniques, allowing for its rapid integration into volume manufacturing using standard tools and materials.
When they say rapid integration, they mean it. AMD will gradually begin using this technique to manufacture its 90nm Athlon 64 processors in the vague-but-immediate time window of "the first half of 2005." IBM will bring the technology to Power PC processors in the same time frame.
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