Athlon 64 journeys to Venice

— 9:54 AM on April 4, 2005

The folks at X-bit Labs have posted a quick review of the new E3 stepping of the Athlon 64, code-named Venice. This is a second revision of the Athlon 64 at 90nm, complete with the expected additions we first reported over a year ago. Those include SSE3 support, better data prefetch, and a more flexible DRAM controller with improved compatibility for DDR400 memory modules. The E3 chips use AMD's version of strained silicon in addition to Silicon-on-Insulator (SOI) technology to keep the electrons flowing, and the two combine to produce a higher clock speed ceiling; the X-bit folks reached over 2.8GHz with their chip. Clock for clock, Venice slightly outperforms its 130nm predecessor, Newcastle, probably in large part due to Venice's enhanced prefetching of data into L2 cache.

We're working on snagging one of these puppies to review ourselves, but right now, we have some even more interesting E3-step processors on the bench.

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