Ars explains Xbox 360 CPU architecture

— 2:02 AM on June 2, 2005

Ars Technica's Jon Stokes has put together a detailed look at the Xbox 360's processor architecture that's all but guaranteed to PYAITK. It's not for the faint of heart, though. You might want to grab a coffee and perhaps a pastry before tackling it.

Instead of spending hardware on an instruction window that looks for ILP at run-time, the Xenon instead relies on the programmer to structure the code stream at compile time so that it contains a high level of thread-level parallelism (TLP). In order to take advantage of the high level of TLP that the Xenon expects programmers to have worked into their Xbox 360 applications, the processor groups its large number of execution units into three separate cores, each of which individually contains a relatively small number of execution units. The many parallel threads out of which the programmer has woven the code stream are then scheduled to run on those separate cores.
For a look at the Xbox 360 CPU's partner in crime, check out our coverage of the upcoming console's graphics chip.
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