Next-gen CPU design aims to increase efficiency

— 2:14 AM on October 5, 2005

There’s an excellent article at Sci-Tech that discusses the inherent difficulty in pushing forward with x86-based dual-core designs, and details a DARPA-funded, next-generation CPU architecture initiative currently underway at the University of Texas at Austin. The new architecture is nicknamed Trips (Teraop Reliable Intelligently Adaptive Processing System); its designers hope it will prove far more scalable and parallelism-friendly than current x86 CPU and compiler designs, while consuming only minimal amounts of additional power. University of Texas computer-science professor Doug Burger explains:

"The industry is running into a programmability wall, passing the buck to software and hoping the programmer will be able to write codes for their systems," he says.

Burger and his colleagues hope to solve these problems with a new microprocessor and instruction set architecture called Trips, or the Teraop Reliable Intelligently Adaptive Processing System. "Our goal is to exploit concurrency, whether it's given to you by the programmer or not," he says.

The Trips architecture is designed to pass code in blocks up to 128 instructions long, with all 128 instructions visible to the processor simultaneously. Multiple instructions can be combined within a block if they operate on the same target and use the same operation, instructions operate as soon as the necessary inputs arrive, and the results of an instruction are immediately available for use by the next instruction without the need to store them in a register first.

Trips is designed to operate well when using instruction-level, thread-level, or data-level parallelism, and should scale well across scientific, commercial, and embedded applications. IBM is producing the first prototype CPUs and is supposed to deliver them by February of 2006. These first-generation prototypes will operate at 500MHz and be capable of executing 16-instructions per cycle; DARPA’s target is to produce 10GHz CPUs capable of executing one teraop by 2012.

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