Intel rips up server roadmaps


— 9:58 AM on October 26, 2005

I'm a little late on this one, but I'd be remiss not to mention Intel's massive overhaul of its server chip plans. News.com has a summary of the changes, as does EETimes. The biggest news is the cancellation of the future Xeon CPU code-named Whitefield, which Intel was talking about pretty recently at IDF. Whitefield was to be a quad-core version of Intel's new microarchitecture, slated for debut in 2007. Whitefield is replaced on the Intel roadmap by Tigerton, a similar processor that scuttles the front-side bus in favor of a "dedicated high-speed interconnect." If you think that sounds like AMD's HyperTransport, then you can go to the head of the class. However, Tigerton reportedly won't include an on-die memory controller along with the new interconnect. Even so, moving away from the front-side bus should make for better multiprocessor system designs than current Xeons.

News.com has sources claiming that this new interconnect will make its debut in mid-2006 along with the "Dempsey" Xeon. (Dempsey will be based on Intel's Netburst microarchitecture.) If true, that would be quite the change in plans, but I can see why Intel might be motivated to do something different in a hurry.

One big consequence of this new plan is that Itanium gets kicked a little further toward the curb. Tigerton's move to a dedicated interconnect will, News.com says, delay Intel's grand scheme to move the Xeon and Itanium lines to a common chipset and CPU socket. Instead, the Montecito version of Itanium gets pushed back from early '06 to mid-year, and it gets downgraded from a 2GHz target clock speed to 1.6GHz, while its bus speed bumps down from 667MHz to the current 400/533MHz clocks. It may also be forced to wear a funny hat and sit in the corner if it continues to misbehave.

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